📄 cnt_fry.tan.rpt
字号:
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Number of paths to report ; 200 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type ; Slack ; Required Time ; Actual Time ; From ; To ;
+------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------+---------+
; Worst-case tco ; N/A ; None ; 37.300 ns ; data1[2] ; seg[3] ;
; Worst-case minimum tco ; N/A ; None ; 13.100 ns ; cnt6[0] ; scan[2] ;
; Clock Setup: 'clk' ; N/A ; None ; 53.76 MHz ( period = 18.600 ns ) ; dat0[3] ; dat5[0] ;
; Clock Setup: 'clk0' ; N/A ; None ; 62.89 MHz ( period = 15.900 ns ) ; lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; clk1khz ;
+------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------+---------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk0 ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk0' ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+--------------------------------------------------------------+--------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 62.89 MHz ( period = 15.900 ns ) ; lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[9] ; clk1khz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 62.89 MHz ( period = 15.900 ns ) ; lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[8] ; clk1khz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 62.89 MHz ( period = 15.900 ns ) ; lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[7] ; clk1khz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; clk1khz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; clk1khz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; clk1khz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; clk1khz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 68.49 MHz ( period = 14.600 ns ) ; lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; clk1khz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[9] ; clk2hz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[8] ; clk2hz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[7] ; clk2hz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[5] ; clk2hz ; clk0 ; clk0 ; None ; None ; None ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[6] ; clk2hz ; clk0 ; clk0 ; None ; None ; None ;
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