shifter.vhd

完成一个加速器设计

library ieee;   
 use ieee.std_logic_1164.all;  
 use ieee.std_logic_unsigned.all;   
  
 entity dffs is   
     port   
     (      
           
         i,enable,clki  :in  std_logic;   
         o :out std_logic);  
 end dffs;   
    
 architecture behave_dff of dffs is   
  begin 
process(clki)
begin 
 if(clki'event and clki='1')
then 
if enable='1' then

o<=i;
else
o<='0';
end if;
end if;
end process;
end behave_dff;
library ieee;   
 use ieee.std_logic_1164.all;  
 use ieee.std_logic_unsigned.all;   
  
 entity add is   
     port   
     (      
           
         i1,i2,enable,clki  :in  std_logic;   
         o :out std_logic);  
 end add;   
    
 architecture behave_add of add is   
  begin
process(clki)
begin
if(clki'event and clki='1')then   
if enable='1' then
o<=i1 xor i2;
 else
o<='0';
end if;
end if;
end process;
end behave_add;



library ieee;   
 use ieee.std_logic_1164.all;  
 use ieee.std_logic_unsigned.all;   
  
 entity shifter is   
     port   
     (   clk    :in  std_logic;   
         cleari:in std_logic; 
         input  :in  std_logic_vector(3 downto 0);   
         output :out std_logic_vector(6 downto 0));  
 end shifter;   
    
 architecture behave_shifter of shifter is 
  component dffs is   
     port   
     (      
           
         i,enable,clki  :in  std_logic;   
         o :out std_logic);  
 end component;   
component add is   
     port   
     (      
           
         i1,i2,enable,clki  :in  std_logic;   
         o :out std_logic);  
 end component;   
    
    

     signal buffer1,buffer2,buffer3,tmp,choose :std_logic; 
     signal cnt:std_logic_vector(3 downto 0); 
 begin 

  
     process(clk)   
    begin  
         if(clk'event and clk='1') then
               if(cleari='0')then  
               case cnt is
                 when "0000" =>
               cnt<="0001";
               choose<='1';
                 tmp<=input(3);
                output(2)<=buffer1;
                output(1)<=buffer2;
                output(0)<=buffer3;
                 when "0001" =>
               cnt<="0010";    
                tmp<=input(2);
                choose<='1';
               output(2)<=buffer1;
                output(1)<=buffer2;
                output(0)<=buffer3;
                 when "0010" =>
               cnt<="0011";    
                tmp<=input(1);
                choose<='1';
               output(2)<=buffer1;
                output(1)<=buffer2;
                output(0)<=buffer3;
                 when "0011" =>
               cnt<="0100";    
                  tmp<=input(0);
                choose<='1'; 
               output(2)<=buffer1;
                output(1)<=buffer2;
                output(0)<=buffer3;
                 when "0100" =>
               cnt<="0101";    
                 tmp<='0';
                choose<='1';
               output(2)<=buffer1;
                output(1)<=buffer2;
                output(0)<=buffer3;
                 when "0101" =>
               cnt<="0110";    
                  tmp<='0';
                choose<='1';
                 output(2)<=buffer1;
                output(1)<=buffer2;
                output(0)<=buffer3;
                 when "0110" =>
               tmp<='0';
                choose<='1';
                cnt<="0111";    
                output(6 downto 3)<=input(3 downto 0);
                output(2)<=buffer1;
                output(1)<=buffer2;
                output(0)<=buffer3;
                 
                when "0111"=>
                tmp<='0';
                cnt<="1000";
                output(6 downto 3)<=input(3 downto 0);
                output(2)<=buffer1;
                output(1)<=buffer2;
                output(0)<=buffer3;
                when "1000"=>
                cnt<="1001";
                output(6 downto 3)<=input(3 downto 0);
                output(0)<=buffer1;
                output(1)<=buffer2;
                output(2)<=buffer3;
                when others=>
               
               null;
          
            end case;
          else
           cnt<="0000";
           choose<='0';
           end if;
        end if; 
  
    end process; 
u2:add port map(i1=>buffer3,i2=>buffer1,enable=>choose,clki=>clk,o=>buffer2);
u1:add port map(i1=>tmp,i2=>buffer3,enable=>choose,clki=>clk,o=>buffer1);

u3:dffs port map(buffer2,choose,clk,buffer3);
 
 end behave_shifter;