mealy1.map.qmsg

状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 07 16:00:54 2008 " "Info: Processing started: Sun Dec 07 16:00:54 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mealy1 -c mealy1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mealy1 -c mealy1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mealy1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mealy1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mealy1-archmealy " "Info: Found design unit 1: mealy1-archmealy" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mealy1 " "Info: Found entity 1: mealy1" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mealy1 " "Info: Elaborating entity \"mealy1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mealy1\|state 5 " "Info: State machine \"\|mealy1\|state\" contains 5 states" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 11 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|mealy1\|state " "Info: Selected Auto state machine encoding method for state machine \"\|mealy1\|state\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 11 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|mealy1\|state " "Info: Encoding result for state machine \"\|mealy1\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state4 " "Info: Encoded state bit \"state.state4\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state3 " "Info: Encoded state bit \"state.state3\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state2 " "Info: Encoded state bit \"state.state2\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state1 " "Info: Encoded state bit \"state.state1\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state0 " "Info: Encoded state bit \"state.state0\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mealy1\|state.state0 00000 " "Info: State \"\|mealy1\|state.state0\" uses code string \"00000\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mealy1\|state.state1 00011 " "Info: State \"\|mealy1\|state.state1\" uses code string \"00011\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mealy1\|state.state2 00101 " "Info: State \"\|mealy1\|state.state2\" uses code string \"00101\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mealy1\|state.state3 01001 " "Info: State \"\|mealy1\|state.state3\" uses code string \"01001\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mealy1\|state.state4 10001 " "Info: State \"\|mealy1\|state.state4\" uses code string \"10001\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 11 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "state.state0 y\[1\]~reg0 " "Info: Duplicate register \"state.state0\" merged to single register \"y\[1\]~reg0\"" {  } { { "mealy1.vhd" "" { Text "D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "22 " "Info: Implemented 22 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 07 16:00:55 2008 " "Info: Processing ended: Sun Dec 07 16:00:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}