mealy1.map.rpt

状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能

; mealy1.vhd                       ; yes             ; User VHDL File  ; D:/altera/quartus60/实例/米勒型(Mealy)状态机/mealy1.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 14    ;
;     -- Combinational with no register       ; 8     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 6     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 8     ;
;     -- 3 input functions                    ; 2     ;
;     -- 2 input functions                    ; 2     ;
;     -- 1 input functions                    ; 2     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 14    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 6     ;
;                                             ;       ;
; Total registers                             ; 6     ;
; I/O pins                                    ; 8     ;
; Maximum fan-out node                        ; id[1] ;
; Maximum fan-out                             ; 6     ;
; Total fan-out                               ; 58    ;
; Average fan-out                             ; 2.64  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |mealy1                    ; 14 (14)     ; 6            ; 0          ; 8    ; 0            ; 8 (8)        ; 0 (0)             ; 6 (6)            ; 0 (0)           ; 0 (0)      ; |mealy1             ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------+
; State Machine - |mealy1|state                                                           ;
+--------------+--------------+--------------+--------------+--------------+--------------+
; Name         ; state.state4 ; state.state3 ; state.state2 ; state.state1 ; state.state0 ;
+--------------+--------------+--------------+--------------+--------------+--------------+
; state.state0 ; 0            ; 0            ; 0            ; 0            ; 0            ;
; state.state1 ; 0            ; 0            ; 0            ; 1            ; 1            ;
; state.state2 ; 0            ; 0            ; 1            ; 0            ; 1            ;
; state.state3 ; 0            ; 1            ; 0            ; 0            ; 1            ;
; state.state4 ; 1            ; 0            ; 0            ; 0            ; 1            ;
+--------------+--------------+--------------+--------------+--------------+--------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 6     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 6     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Dec 07 16:00:54 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mealy1 -c mealy1
Info: Found 2 design units, including 1 entities, in source file mealy1.vhd
    Info: Found design unit 1: mealy1-archmealy
    Info: Found entity 1: mealy1
Info: Elaborating entity "mealy1" for the top level hierarchy
Info: State machine "|mealy1|state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|mealy1|state"
Info: Encoding result for state machine "|mealy1|state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "state.state4"
        Info: Encoded state bit "state.state3"
        Info: Encoded state bit "state.state2"
        Info: Encoded state bit "state.state1"
        Info: Encoded state bit "state.state0"
    Info: State "|mealy1|state.state0" uses code string "00000"
    Info: State "|mealy1|state.state1" uses code string "00011"
    Info: State "|mealy1|state.state2" uses code string "00101"
    Info: State "|mealy1|state.state3" uses code string "01001"
    Info: State "|mealy1|state.state4" uses code string "10001"
Info: Duplicate registers merged to single register
    Info: Duplicate register "state.state0" merged to single register "y[1]~reg0"
Info: Implemented 22 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 2 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Dec 07 16:00:55 2008
    Info: Elapsed time: 00:00:02