mealy1.tan.rpt

状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能

; N/A   ; None         ; 3.939 ns   ; id[2] ; y[0]~reg0    ; clk      ;
; N/A   ; None         ; 3.891 ns   ; id[2] ; state.state2 ; clk      ;
; N/A   ; None         ; 3.833 ns   ; id[1] ; y[1]~reg0    ; clk      ;
; N/A   ; None         ; 3.719 ns   ; id[3] ; state.state1 ; clk      ;
; N/A   ; None         ; 3.673 ns   ; id[0] ; state.state1 ; clk      ;
; N/A   ; None         ; 3.602 ns   ; id[1] ; state.state1 ; clk      ;
; N/A   ; None         ; 3.599 ns   ; id[2] ; state.state1 ; clk      ;
; N/A   ; None         ; 2.886 ns   ; id[1] ; state.state4 ; clk      ;
+-------+--------------+------------+-------+--------------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 7.170 ns   ; y[1]~reg0 ; y[1] ; clk        ;
; N/A   ; None         ; 7.147 ns   ; y[0]~reg0 ; y[0] ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+-------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To           ; To Clock ;
+---------------+-------------+-----------+-------+--------------+----------+
; N/A           ; None        ; -1.499 ns ; id[1] ; y[1]~reg0    ; clk      ;
; N/A           ; None        ; -1.848 ns ; id[2] ; state.state3 ; clk      ;
; N/A           ; None        ; -1.867 ns ; id[1] ; state.state3 ; clk      ;
; N/A           ; None        ; -1.917 ns ; id[1] ; y[0]~reg0    ; clk      ;
; N/A           ; None        ; -2.332 ns ; id[1] ; state.state4 ; clk      ;
; N/A           ; None        ; -2.954 ns ; id[2] ; y[1]~reg0    ; clk      ;
; N/A           ; None        ; -2.972 ns ; id[0] ; state.state3 ; clk      ;
; N/A           ; None        ; -3.028 ns ; id[0] ; y[1]~reg0    ; clk      ;
; N/A           ; None        ; -3.045 ns ; id[2] ; state.state1 ; clk      ;
; N/A           ; None        ; -3.048 ns ; id[1] ; state.state1 ; clk      ;
; N/A           ; None        ; -3.074 ns ; id[3] ; y[1]~reg0    ; clk      ;
; N/A           ; None        ; -3.119 ns ; id[0] ; state.state1 ; clk      ;
; N/A           ; None        ; -3.165 ns ; id[3] ; state.state1 ; clk      ;
; N/A           ; None        ; -3.199 ns ; id[3] ; state.state3 ; clk      ;
; N/A           ; None        ; -3.207 ns ; id[3] ; y[0]~reg0    ; clk      ;
; N/A           ; None        ; -3.234 ns ; id[0] ; y[0]~reg0    ; clk      ;
; N/A           ; None        ; -3.335 ns ; id[2] ; y[0]~reg0    ; clk      ;
; N/A           ; None        ; -3.337 ns ; id[2] ; state.state2 ; clk      ;
; N/A           ; None        ; -3.511 ns ; id[1] ; state.state2 ; clk      ;
; N/A           ; None        ; -3.611 ns ; id[0] ; state.state2 ; clk      ;
; N/A           ; None        ; -3.622 ns ; id[3] ; state.state4 ; clk      ;
; N/A           ; None        ; -3.649 ns ; id[0] ; state.state4 ; clk      ;
; N/A           ; None        ; -3.800 ns ; id[2] ; state.state4 ; clk      ;
; N/A           ; None        ; -3.921 ns ; id[3] ; state.state2 ; clk      ;
+---------------+-------------+-----------+-------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Dec 07 16:01:02 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mealy1 -c mealy1
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 238.95 MHz between source register "state.state2" and destination register "state.state2" (period= 4.185 ns)
    Info: + Longest register to register delay is 3.476 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N9; Fanout = 2; REG Node = 'state.state2'
        Info: 2: + IC(1.365 ns) + CELL(0.511 ns) = 1.876 ns; Loc. = LC_X1_Y7_N4; Fanout = 2; COMB Node = 'Selector5~157'
        Info: 3: + IC(0.796 ns) + CELL(0.804 ns) = 3.476 ns; Loc. = LC_X1_Y7_N9; Fanout = 2; REG Node = 'state.state2'
        Info: Total cell delay = 1.315 ns ( 37.83 % )
        Info: Total interconnect delay = 2.161 ns ( 62.17 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.681 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N9; Fanout = 2; REG Node = 'state.state2'
            Info: Total cell delay = 2.081 ns ( 56.53 % )
            Info: Total interconnect delay = 1.600 ns ( 43.47 % )
        Info: - Longest clock path from clock "clk" to source register is 3.681 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N9; Fanout = 2; REG Node = 'state.state2'
            Info: Total cell delay = 2.081 ns ( 56.53 % )
            Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "state.state2" (data pin = "id[3]", clock pin = "clk") is 4.475 ns
    Info: + Longest pin to register delay is 7.823 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_E1; Fanout = 4; PIN Node = 'id[3]'
        Info: 2: + IC(3.409 ns) + CELL(0.740 ns) = 5.281 ns; Loc. = LC_X1_Y7_N8; Fanout = 2; COMB Node = 'Selector2~66'
        Info: 3: + IC(0.742 ns) + CELL(0.200 ns) = 6.223 ns; Loc. = LC_X1_Y7_N4; Fanout = 2; COMB Node = 'Selector5~157'
        Info: 4: + IC(0.796 ns) + CELL(0.804 ns) = 7.823 ns; Loc. = LC_X1_Y7_N9; Fanout = 2; REG Node = 'state.state2'
        Info: Total cell delay = 2.876 ns ( 36.76 % )
        Info: Total interconnect delay = 4.947 ns ( 63.24 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N9; Fanout = 2; REG Node = 'state.state2'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
Info: tco from clock "clk" to destination pin "y[1]" through register "y[1]~reg0" is 7.170 ns
    Info: + Longest clock path from clock "clk" to source register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y6_N2; Fanout = 3; REG Node = 'y[1]~reg0'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 3.113 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y6_N2; Fanout = 3; REG Node = 'y[1]~reg0'
        Info: 2: + IC(0.791 ns) + CELL(2.322 ns) = 3.113 ns; Loc. = PIN_G1; Fanout = 0; PIN Node = 'y[1]'
        Info: Total cell delay = 2.322 ns ( 74.59 % )
        Info: Total interconnect delay = 0.791 ns ( 25.41 % )
Info: th for register "y[1]~reg0" (data pin = "id[1]", clock pin = "clk") is -1.499 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y6_N2; Fanout = 3; REG Node = 'y[1]~reg0'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.401 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_D2; Fanout = 6; PIN Node = 'id[1]'
        Info: 2: + IC(3.086 ns) + CELL(1.183 ns) = 5.401 ns; Loc. = LC_X1_Y6_N2; Fanout = 3; REG Node = 'y[1]~reg0'
        Info: Total cell delay = 2.315 ns ( 42.86 % )
        Info: Total interconnect delay = 3.086 ns ( 57.14 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Dec 07 16:01:02 2008
    Info: Elapsed time: 00:00:01