s_machine.tan.rpt

来自「状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能」· RPT 代码 · 共 222 行 · 第 1/2 页

; N/A   ; None         ; 2.180 ns   ; State_inputs[1] ; c_s.st3 ; clk      ;
; N/A   ; None         ; 1.945 ns   ; State_inputs[0] ; c_s.st0 ; clk      ;
; N/A   ; None         ; 1.941 ns   ; State_inputs[0] ; c_s.st2 ; clk      ;
; N/A   ; None         ; 1.937 ns   ; State_inputs[0] ; c_s.st3 ; clk      ;
; N/A   ; None         ; 1.933 ns   ; State_inputs[0] ; c_s.st1 ; clk      ;
+-------+--------------+------------+-----------------+---------+----------+


+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+---------+-----------------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To              ; From Clock ;
+-------+--------------+------------+---------+-----------------+------------+
; N/A   ; None         ; 8.694 ns   ; c_s.st2 ; Comb_outputs[0] ; clk        ;
; N/A   ; None         ; 8.482 ns   ; c_s.st1 ; Comb_outputs[1] ; clk        ;
; N/A   ; None         ; 8.162 ns   ; c_s.st0 ; Comb_outputs[1] ; clk        ;
; N/A   ; None         ; 8.161 ns   ; c_s.st0 ; Comb_outputs[0] ; clk        ;
+-------+--------------+------------+---------+-----------------+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+-----------------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From            ; To      ; To Clock ;
+---------------+-------------+-----------+-----------------+---------+----------+
; N/A           ; None        ; -1.379 ns ; State_inputs[0] ; c_s.st1 ; clk      ;
; N/A           ; None        ; -1.383 ns ; State_inputs[0] ; c_s.st3 ; clk      ;
; N/A           ; None        ; -1.387 ns ; State_inputs[0] ; c_s.st2 ; clk      ;
; N/A           ; None        ; -1.391 ns ; State_inputs[0] ; c_s.st0 ; clk      ;
; N/A           ; None        ; -1.626 ns ; State_inputs[1] ; c_s.st3 ; clk      ;
; N/A           ; None        ; -1.627 ns ; State_inputs[1] ; c_s.st1 ; clk      ;
; N/A           ; None        ; -1.629 ns ; State_inputs[1] ; c_s.st2 ; clk      ;
; N/A           ; None        ; -1.633 ns ; State_inputs[1] ; c_s.st0 ; clk      ;
+---------------+-------------+-----------+-----------------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Dec 23 00:16:46 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off s_machine -c s_machine
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 304.04 MHz between source register "c_s.st1" and destination register "c_s.st2"
    Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.788 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N5; Fanout = 3; REG Node = 'c_s.st1'
            Info: 2: + IC(0.984 ns) + CELL(0.804 ns) = 1.788 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'c_s.st2'
            Info: Total cell delay = 0.804 ns ( 44.97 % )
            Info: Total interconnect delay = 0.984 ns ( 55.03 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.681 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'c_s.st2'
                Info: Total cell delay = 2.081 ns ( 56.53 % )
                Info: Total interconnect delay = 1.600 ns ( 43.47 % )
            Info: - Longest clock path from clock "clk" to source register is 3.681 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N5; Fanout = 3; REG Node = 'c_s.st1'
                Info: Total cell delay = 2.081 ns ( 56.53 % )
                Info: Total interconnect delay = 1.600 ns ( 43.47 % )
        Info: + Micro clock to output delay of source is 0.376 ns
        Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "c_s.st0" (data pin = "State_inputs[1]", clock pin = "clk") is 2.187 ns
    Info: + Longest pin to register delay is 5.535 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_D2; Fanout = 4; PIN Node = 'State_inputs[1]'
        Info: 2: + IC(3.342 ns) + CELL(1.061 ns) = 5.535 ns; Loc. = LC_X1_Y7_N2; Fanout = 4; REG Node = 'c_s.st0'
        Info: Total cell delay = 2.193 ns ( 39.62 % )
        Info: Total interconnect delay = 3.342 ns ( 60.38 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N2; Fanout = 4; REG Node = 'c_s.st0'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
Info: tco from clock "clk" to destination pin "Comb_outputs[0]" through register "c_s.st2" is 8.694 ns
    Info: + Longest clock path from clock "clk" to source register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'c_s.st2'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.637 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'c_s.st2'
        Info: 2: + IC(0.969 ns) + CELL(0.740 ns) = 1.709 ns; Loc. = LC_X1_Y7_N3; Fanout = 1; COMB Node = 'Comb_outputs~1'
        Info: 3: + IC(0.606 ns) + CELL(2.322 ns) = 4.637 ns; Loc. = PIN_D3; Fanout = 0; PIN Node = 'Comb_outputs[0]'
        Info: Total cell delay = 3.062 ns ( 66.03 % )
        Info: Total interconnect delay = 1.575 ns ( 33.97 % )
Info: th for register "c_s.st1" (data pin = "State_inputs[0]", clock pin = "clk") is -1.379 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N5; Fanout = 3; REG Node = 'c_s.st1'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.281 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_G2; Fanout = 4; PIN Node = 'State_inputs[0]'
        Info: 2: + IC(2.966 ns) + CELL(1.183 ns) = 5.281 ns; Loc. = LC_X1_Y7_N5; Fanout = 3; REG Node = 'c_s.st1'
        Info: Total cell delay = 2.315 ns ( 43.84 % )
        Info: Total interconnect delay = 2.966 ns ( 56.16 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Dec 23 00:16:47 2008
    Info: Elapsed time: 00:00:02