s_machine.tan.qmsg

状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register c_s.st1 c_s.st2 304.04 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 304.04 MHz between source register \"c_s.st1\" and destination register \"c_s.st2\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.788 ns + Longest register register " "Info: + Longest register to register delay is 1.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c_s.st1 1 REG LC_X1_Y7_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N5; Fanout = 3; REG Node = 'c_s.st1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_s.st1 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.804 ns) 1.788 ns c_s.st2 2 REG LC_X1_Y7_N9 3 " "Info: 2: + IC(0.984 ns) + CELL(0.804 ns) = 1.788 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'c_s.st2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.788 ns" { c_s.st1 c_s.st2 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.804 ns ( 44.97 % ) " "Info: Total cell delay = 0.804 ns ( 44.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.984 ns ( 55.03 % ) " "Info: Total interconnect delay = 0.984 ns ( 55.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.788 ns" { c_s.st1 c_s.st2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.788 ns" { c_s.st1 c_s.st2 } { 0.000ns 0.984ns } { 0.000ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_H5 4 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns c_s.st2 2 REG LC_X1_Y7_N9 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'c_s.st2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { clk c_s.st2 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st2 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.681 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_H5 4 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns c_s.st1 2 REG LC_X1_Y7_N5 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N5; Fanout = 3; REG Node = 'c_s.st1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { clk c_s.st1 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st1 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st2 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st1 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.788 ns" { c_s.st1 c_s.st2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.788 ns" { c_s.st1 c_s.st2 } { 0.000ns 0.984ns } { 0.000ns 0.804ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st2 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st1 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_s.st2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { c_s.st2 } {  } {  } } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "c_s.st0 State_inputs\[1\] clk 2.187 ns register " "Info: tsu for register \"c_s.st0\" (data pin = \"State_inputs\[1\]\", clock pin = \"clk\") is 2.187 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.535 ns + Longest pin register " "Info: + Longest pin to register delay is 5.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns State_inputs\[1\] 1 PIN PIN_D2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_D2; Fanout = 4; PIN Node = 'State_inputs\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { State_inputs[1] } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.342 ns) + CELL(1.061 ns) 5.535 ns c_s.st0 2 REG LC_X1_Y7_N2 4 " "Info: 2: + IC(3.342 ns) + CELL(1.061 ns) = 5.535 ns; Loc. = LC_X1_Y7_N2; Fanout = 4; REG Node = 'c_s.st0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.403 ns" { State_inputs[1] c_s.st0 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 39.62 % ) " "Info: Total cell delay = 2.193 ns ( 39.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.342 ns ( 60.38 % ) " "Info: Total interconnect delay = 3.342 ns ( 60.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.535 ns" { State_inputs[1] c_s.st0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.535 ns" { State_inputs[1] State_inputs[1]~combout c_s.st0 } { 0.000ns 0.000ns 3.342ns } { 0.000ns 1.132ns 1.061ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_H5 4 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns c_s.st0 2 REG LC_X1_Y7_N2 4 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N2; Fanout = 4; REG Node = 'c_s.st0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { clk c_s.st0 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st0 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.535 ns" { State_inputs[1] c_s.st0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.535 ns" { State_inputs[1] State_inputs[1]~combout c_s.st0 } { 0.000ns 0.000ns 3.342ns } { 0.000ns 1.132ns 1.061ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st0 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Comb_outputs\[0\] c_s.st2 8.694 ns register " "Info: tco from clock \"clk\" to destination pin \"Comb_outputs\[0\]\" through register \"c_s.st2\" is 8.694 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.681 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_H5 4 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns c_s.st2 2 REG LC_X1_Y7_N9 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'c_s.st2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { clk c_s.st2 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st2 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.637 ns + Longest register pin " "Info: + Longest register to pin delay is 4.637 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c_s.st2 1 REG LC_X1_Y7_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'c_s.st2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_s.st2 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.969 ns) + CELL(0.740 ns) 1.709 ns Comb_outputs~1 2 COMB LC_X1_Y7_N3 1 " "Info: 2: + IC(0.969 ns) + CELL(0.740 ns) = 1.709 ns; Loc. = LC_X1_Y7_N3; Fanout = 1; COMB Node = 'Comb_outputs~1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.709 ns" { c_s.st2 Comb_outputs~1 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(2.322 ns) 4.637 ns Comb_outputs\[0\] 3 PIN PIN_D3 0 " "Info: 3: + IC(0.606 ns) + CELL(2.322 ns) = 4.637 ns; Loc. = PIN_D3; Fanout = 0; PIN Node = 'Comb_outputs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.928 ns" { Comb_outputs~1 Comb_outputs[0] } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.062 ns ( 66.03 % ) " "Info: Total cell delay = 3.062 ns ( 66.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.575 ns ( 33.97 % ) " "Info: Total interconnect delay = 1.575 ns ( 33.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.637 ns" { c_s.st2 Comb_outputs~1 Comb_outputs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.637 ns" { c_s.st2 Comb_outputs~1 Comb_outputs[0] } { 0.000ns 0.969ns 0.606ns } { 0.000ns 0.740ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st2 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.637 ns" { c_s.st2 Comb_outputs~1 Comb_outputs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.637 ns" { c_s.st2 Comb_outputs~1 Comb_outputs[0] } { 0.000ns 0.969ns 0.606ns } { 0.000ns 0.740ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "c_s.st1 State_inputs\[0\] clk -1.379 ns register " "Info: th for register \"c_s.st1\" (data pin = \"State_inputs\[0\]\", clock pin = \"clk\") is -1.379 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_H5 4 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns c_s.st1 2 REG LC_X1_Y7_N5 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N5; Fanout = 3; REG Node = 'c_s.st1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { clk c_s.st1 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st1 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.281 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.281 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns State_inputs\[0\] 1 PIN PIN_G2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_G2; Fanout = 4; PIN Node = 'State_inputs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { State_inputs[0] } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.966 ns) + CELL(1.183 ns) 5.281 ns c_s.st1 2 REG LC_X1_Y7_N5 3 " "Info: 2: + IC(2.966 ns) + CELL(1.183 ns) = 5.281 ns; Loc. = LC_X1_Y7_N5; Fanout = 3; REG Node = 'c_s.st1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.149 ns" { State_inputs[0] c_s.st1 } "NODE_NAME" } } { "s_machine.vhd" "" { Text "D:/altera/quartus60/实例/状态机/s_machine.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.315 ns ( 43.84 % ) " "Info: Total cell delay = 2.315 ns ( 43.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.966 ns ( 56.16 % ) " "Info: Total interconnect delay = 2.966 ns ( 56.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.281 ns" { State_inputs[0] c_s.st1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.281 ns" { State_inputs[0] State_inputs[0]~combout c_s.st1 } { 0.000ns 0.000ns 2.966ns } { 0.000ns 1.132ns 1.183ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk c_s.st1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk clk~combout c_s.st1 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.281 ns" { State_inputs[0] c_s.st1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.281 ns" { State_inputs[0] State_inputs[0]~combout c_s.st1 } { 0.000ns 0.000ns 2.966ns } { 0.000ns 1.132ns 1.183ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 23 00:16:47 2008 " "Info: Processing ended: Tue Dec 23 00:16:47 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}