s_machine.vhd

来自「状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能」· VHDL 代码 · 共 48 行

Library ieee;
Use ieee.std_logic_1164.all;
Entity s_machine is
Port(clk,rst:in std_logic;
State_inputs:in std_logic_vector(1 downto 0);
Comb_outputs:out std_logic_vector(1 downto 0));
End entity s_machine;

Architecture one of s_machine is
Type states is(st0,st1,st2,st3);
Signal c_s,n_s:states;
begin
P1:process(rst,clk)
Begin
If rst='1' then 
C_s<=st0;
elsif (clk'event and clk='1') then
C_s<=n_s;
End if;
End process p1;

P2:process(c_s,state_inputs)
Begin
Case c_s is
When st0=>comb_outputs<="00";
If state_inputs="00" then
n_s<=st0;
else n_s<=st1;
end if;
when st1=>comb_outputs<="01";
if state_inputs="00" then 
n_s<=st1;
else n_s<=st2;
end if;
when st2=>comb_outputs<="10";
if state_inputs="11" then
n_s<=st2;
else n_s<=st3;
end if;
when st3=>comb_outputs<="11";
if state_inputs="11" then 
n_s<=st3;
else n_s<=st0;
end if;
end case;
end process p2;
end architecture one;