📄 decoder_3_8.tan.rpt
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Timing Analyzer report for decoder_3_8
Tue Dec 23 07:28:58 2008
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 5.394 ns ; S1 ; Q[7] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM570F256C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 5.394 ns ; S1 ; Q[7] ;
; N/A ; None ; 5.341 ns ; S1 ; Q[4] ;
; N/A ; None ; 5.307 ns ; S3 ; Q[7] ;
; N/A ; None ; 5.254 ns ; S3 ; Q[4] ;
; N/A ; None ; 5.247 ns ; A ; Q[6] ;
; N/A ; None ; 5.228 ns ; C ; Q[6] ;
; N/A ; None ; 5.212 ns ; A ; Q[7] ;
; N/A ; None ; 5.177 ns ; A ; Q[4] ;
; N/A ; None ; 5.164 ns ; B ; Q[6] ;
; N/A ; None ; 5.158 ns ; C ; Q[4] ;
; N/A ; None ; 5.128 ns ; B ; Q[7] ;
; N/A ; None ; 5.094 ns ; B ; Q[4] ;
; N/A ; None ; 5.092 ns ; S2 ; Q[7] ;
; N/A ; None ; 5.044 ns ; S1 ; Q[6] ;
; N/A ; None ; 5.043 ns ; C ; Q[7] ;
; N/A ; None ; 5.039 ns ; S2 ; Q[4] ;
; N/A ; None ; 5.024 ns ; S1 ; Q[0] ;
; N/A ; None ; 4.957 ns ; S3 ; Q[6] ;
; N/A ; None ; 4.937 ns ; S3 ; Q[0] ;
; N/A ; None ; 4.833 ns ; A ; Q[0] ;
; N/A ; None ; 4.751 ns ; B ; Q[0] ;
; N/A ; None ; 4.742 ns ; S2 ; Q[6] ;
; N/A ; None ; 4.722 ns ; S2 ; Q[0] ;
; N/A ; None ; 4.683 ns ; C ; Q[0] ;
; N/A ; None ; 4.617 ns ; S1 ; Q[1] ;
; N/A ; None ; 4.613 ns ; S1 ; Q[5] ;
; N/A ; None ; 4.613 ns ; S1 ; Q[3] ;
; N/A ; None ; 4.612 ns ; S1 ; Q[2] ;
; N/A ; None ; 4.530 ns ; S3 ; Q[1] ;
; N/A ; None ; 4.526 ns ; S3 ; Q[5] ;
; N/A ; None ; 4.526 ns ; S3 ; Q[3] ;
; N/A ; None ; 4.525 ns ; S3 ; Q[2] ;
; N/A ; None ; 4.431 ns ; A ; Q[3] ;
; N/A ; None ; 4.430 ns ; A ; Q[2] ;
; N/A ; None ; 4.429 ns ; A ; Q[1] ;
; N/A ; None ; 4.427 ns ; A ; Q[5] ;
; N/A ; None ; 4.347 ns ; B ; Q[3] ;
; N/A ; None ; 4.347 ns ; B ; Q[2] ;
; N/A ; None ; 4.343 ns ; B ; Q[1] ;
; N/A ; None ; 4.342 ns ; B ; Q[5] ;
; N/A ; None ; 4.315 ns ; S2 ; Q[1] ;
; N/A ; None ; 4.311 ns ; S2 ; Q[5] ;
; N/A ; None ; 4.311 ns ; S2 ; Q[3] ;
; N/A ; None ; 4.310 ns ; S2 ; Q[2] ;
; N/A ; None ; 4.276 ns ; C ; Q[1] ;
; N/A ; None ; 4.273 ns ; C ; Q[5] ;
; N/A ; None ; 4.269 ns ; C ; Q[2] ;
; N/A ; None ; 4.268 ns ; C ; Q[3] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Tue Dec 23 07:28:58 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off decoder_3_8 -c decoder_3_8
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "S1" to destination pin "Q[7]" is 5.394 ns
Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_F3; Fanout = 1; PIN Node = 'S1'
Info: 2: + IC(0.761 ns) + CELL(0.462 ns) = 1.931 ns; Loc. = LC_X1_Y7_N4; Fanout = 8; COMB Node = 'process0~78'
Info: 3: + IC(0.531 ns) + CELL(0.319 ns) = 2.781 ns; Loc. = LC_X1_Y7_N0; Fanout = 1; COMB Node = 'Q~119'
Info: 4: + IC(1.159 ns) + CELL(1.454 ns) = 5.394 ns; Loc. = PIN_G2; Fanout = 0; PIN Node = 'Q[7]'
Info: Total cell delay = 2.943 ns ( 54.56 % )
Info: Total interconnect delay = 2.451 ns ( 45.44 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Dec 23 07:28:58 2008
Info: Elapsed time: 00:00:01
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