decoder_3_8.vhd

利用CASE语句的3-8译码器,3个为数据输入,3个为控制端,分别为S1,S2,S3,输出数据为八位

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder_3_8 IS
PORT ( C,B,A: IN STD_LOGIC;
       S1,S2,S3: IN STD_LOGIC;
       Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY decoder_3_8;
ARCHITECTURE ONE OF decoder_3_8 IS
SIGNAL temp_datain: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
   temp_datain <=C&B&A;
    PROCESS(S1,S2,S3,temp_datain )
 BEGIN

   
     IF(S1='1'  AND S2='0' AND S3='0') THEN
      CASE temp_datain IS
      WHEN "000"=> Q <= "11111110";
      WHEN "001"=> Q <= "11111101";
      WHEN "010"=> Q <= "11111011";
      WHEN "011"=> Q <= "11110111";
      WHEN "100"=> Q <= "11101111";
      WHEN "101"=> Q <= "11011111";
      WHEN "110"=> Q <= "10111111";
      WHEN "111"=> Q <= "01111111";
      WHEN OTHERS => Q <="XXXXXXXX";
      END CASE;
     ELSE
       Q<="11111111";
     END IF ;
   END PROCESS ;
END ARCHITECTURE ONE ;