rl_shift.map.rpt

带有同步预置的加载左右移位寄存器VHDL源代码

; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                              ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                 ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------------+
; RL_SHIFT.vhd                     ; yes             ; User VHDL File  ; D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Total logic elements                        ; 9       ;
;     -- Combinational with no register       ; 1       ;
;     -- Register only                        ; 0       ;
;     -- Combinational with a register        ; 8       ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 0       ;
;     -- 3 input functions                    ; 9       ;
;     -- 2 input functions                    ; 0       ;
;     -- 1 input functions                    ; 0       ;
;     -- 0 input functions                    ; 0       ;
;         -- Combinational cells for routing  ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 9       ;
;     -- arithmetic mode                      ; 0       ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 8       ;
;     -- asynchronous clear/load mode         ; 0       ;
;                                             ;         ;
; Total registers                             ; 8       ;
; I/O pins                                    ; 22      ;
; Maximum fan-out node                        ; MODE[1] ;
; Maximum fan-out                             ; 9       ;
; Total fan-out                               ; 75      ;
; Average fan-out                             ; 2.42    ;
+---------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |RL_SHIFT                  ; 9 (9)       ; 8            ; 0          ; 22   ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; 0 (0)           ; 0 (0)      ; |RL_SHIFT           ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 8     ;
; Number of registers using Synchronous Clear  ; 8     ;
; Number of registers using Synchronous Load   ; 8     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |RL_SHIFT|TEMP[0]          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Dec 22 23:58:46 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RL_SHIFT -c RL_SHIFT
Info: Found 2 design units, including 1 entities, in source file RL_SHIFT.vhd
    Info: Found design unit 1: RL_SHIFT-ONE
    Info: Found entity 1: RL_SHIFT
Info: Elaborating entity "RL_SHIFT" for the top level hierarchy
Info: Implemented 31 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 8 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Dec 22 23:58:47 2008
    Info: Elapsed time: 00:00:02