notetabs.vhd

来自「基于MUXPLUS2的VHDL程序」· VHDL 代码 · 共 37 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY NoteTabs IS
    PORT ( clk    : IN STD_LOGIC;
ENA:IN STD_LOGIC_VECTOR (1 DOWNTO 0);
           ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END;
ARCHITECTURE one OF NoteTabs IS
COMPONENT MUSIC                --音符数据ROM
 PORT(address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	  inclock : IN STD_LOGIC ;
	        q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT;
    SIGNAL Counter :  STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
    CNT8 : PROCESS(clk,Counter)
    BEGIN
        
           
           IF (clk'EVENT AND clk = '1') THEN
              IF ENA="00"  THEN 
                IF Counter=215   THEN Counter <= "10001011";
                  ELSE  Counter <=Counter+1;
                  END IF;
              ELSIF ENA="01" THEN
                  IF  Counter=138  THEN Counter <= "00000000";
                  ELSE  Counter <=Counter+1;
                  END IF;
            END IF;
            END IF;
           END PROCESS;
 u1 : MUSIC PORT MAP(address=>Counter , q=>ToneIndex, inclock=>clk); 
  END;