keylock.vhd

时间以60分种为一个周期 电子钟的格式为：XX XX XX

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_ARITH.ALL ; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; 
LIBRARY altera; 
USE altera.maxplus2.ALL; 

ENTITY KEYLOCK IS
PORT ( 
CLK_40M : IN STD_LOGIC ; --system original cKEY_L 40M 
CLK_SCAN : OUT STD_LOGIC_VECTOR (3 downto 0) ; --scan sequence 
KEY_IN : IN STD_LOGIC_VECTOR (3 downto 0) ; --KEY IN button code 
KEY_L : IN STD_LOGIC ; 
KEY_UNL : IN STD_LOGIC ;
BACK:IN  STD_LOGIC ; --BACK 
ENLOCK : OUT STD_LOGIC ; --1:KEY_L, 0:KEY_UNL 
SELOUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ; --SELOUT SCAN
SEGOUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) -- SEG7 Display 
); 
END ENTITY KEYLOCK;
ARCHITECTURE ART OF KEYLOCK IS
COMPONENT COUNTER  --元件例化 计数器
  PORT(CLK_40M:IN STD_LOGIC;
     CLK:OUT STD_LOGIC;
     CLK_KEYBOARD:BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);
     CLK_DISPLAY:OUT  STD_LOGIC_VECTOR(1 DOWNTO 0);
     CLK_SCAN:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
 END COMPONENT ;
 COMPONENT KEYBOARD   --元件例化  键盘
  PORT(CLK:IN STD_LOGIC;
     CLK_KEYBOARD:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
     KEY_IN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
     KEY_L,KEY_UNL:IN STD_LOGIC;
     BACK:IN STD_LOGIC;
     FN:OUT STD_LOGIC;
     CLEAR:OUT STD_LOGIC;
     N:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
 END COMPONENT ;
COMPONENT CONTROLER    --元件例化   控制器
PORT(CLK:IN STD_LOGIC;
     FN:IN STD_LOGIC;
     KEY_L,KEY_UNL:IN STD_LOGIC;
     BACK:IN STD_LOGIC;
     N:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
     CLK_DISPLAY: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
     CLEAR:IN STD_LOGIC;
     ENLOCK:OUT STD_LOGIC;
     DB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT ;
COMPONENT DISPLAY    --元件例化   显示
PORT(DB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
     CLK_DISPLAY: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
     SEGOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
     SELOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT ;
--**********************************************
--内部信号
SIGNAL CLKL:STD_LOGIC;
SIGNAL CLK_KEYBOARDL:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL CLK_DISPLAYL:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL NL:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DBL:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL FNL:STD_LOGIC;
SIGNAL CLEARL:STD_LOGIC;

--************************************************
BEGIN 
--各模块的结合
U1:COUNTER PORT MAP(CLK_40M=>CLK_40M,CLK=>CLKL,        CLK_KEYBOARD=>CLK_KEYBOARDL,CLK_DISPLAY=>CLK_DISPLAYL,
        CLK_SCAN=>CLK_SCAN);               --计数器模块
U2:KEYBOARD 
PORT MAP(CLK=>CLKL,CLK_KEYBOARD=>CLK_KEYBOARDL,
                     KEY_IN=>KEY_IN,KEY_L=>KEY_L,                  KEY_UNL=>KEY_UNL,BACK=>BACK,FN=>FNL,CLEAR=>CLEARL,
                     N=>NL);                   --键盘模块
U3:CONTROLER    --电路控制模块
PORT MAP(CLK=>CLKL,FN=>FNL,KEY_L=>KEY_L,KEY_UNL=>KEY_UNL,
                      BACK=>BACK,N=>NL, 
                      CLK_DISPLAY=>CLK_DISPLAYL, CLEAR=>CLEARL,
                      ENLOCK=>ENLOCK,DB=>DBL);
U4:DISPLAY                                   --扫描显示模块
PORT MAP(DB=>DBL,CLK_DISPLAY=>CLK_DISPLAYL,SEGOUT=>SEGOUT,
SELOUT=>SELOUT);
End ARCHITECTURE ART;