keylock.tan.qmsg

时间以60分种为一个周期 电子钟的格式为：XX XX XX

{ "Info" "ITDB_TH_RESULT" "KEYBOARD:U2\|\\key_decoder:R0 KEY_L CLK_40M 1.200 ns register " "Info: th for register \"KEYBOARD:U2\|\\key_decoder:R0\" (data pin = \"KEY_L\", clock pin = \"CLK_40M\") is 1.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40M destination 6.700 ns + Longest register " "Info: + Longest clock path from clock \"CLK_40M\" to destination register is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK_40M 1 CLK PIN_55 23 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 23; CLK Node = 'CLK_40M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "" { CLK_40M } "NODE_NAME" } "" } } { "KEYLOCK.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYLOCK.VHD" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns counter:U1\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] 2 REG LC1_A24 50 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_A24; Fanout = 50; REG Node = 'counter:U1\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "0.900 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(0.000 ns) 6.700 ns KEYBOARD:U2\|\\key_decoder:R0 3 REG LC1_A36 3 " "Info: 3: + IC(3.800 ns) + CELL(0.000 ns) = 6.700 ns; Loc. = LC1_A36; Fanout = 3; REG Node = 'KEYBOARD:U2\|\\key_decoder:R0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "3.800 ns" { counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|\key_decoder:R0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 37.31 % ) " "Info: Total cell delay = 2.500 ns ( 37.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 62.69 % ) " "Info: Total interconnect delay = 4.200 ns ( 62.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "6.700 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|\key_decoder:R0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { CLK_40M CLK_40M~out counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|\key_decoder:R0 } { 0.000ns 0.000ns 0.400ns 3.800ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns KEY_L 1 PIN PIN_8 4 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 4; PIN Node = 'KEY_L'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_