keylock.tan.qmsg

时间以60分种为一个周期 电子钟的格式为：XX XX XX

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "KEYBOARD:U2\|N\[0\] " "Info: Detected ripple clock \"KEYBOARD:U2\|N\[0\]\" as buffer" {  } { { "KEYBOARD.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYBOARD.VHD" 65 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KEYBOARD:U2\|N\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "KEYBOARD:U2\|N\[1\] " "Info: Detected ripple clock \"KEYBOARD:U2\|N\[1\]\" as buffer" {  } { { "KEYBOARD.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYBOARD.VHD" 65 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KEYBOARD:U2\|N\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "KEYBOARD:U2\|N\[2\] " "Info: Detected ripple clock \"KEYBOARD:U2\|N\[2\]\" as buffer" {  } { { "KEYBOARD.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYBOARD.VHD" 65 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KEYBOARD:U2\|N\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "KEYBOARD:U2\|N\[3\] " "Info: Detected ripple clock \"KEYBOARD:U2\|N\[3\]\" as buffer" {  } { { "KEYBOARD.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYBOARD.VHD" 65 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KEYBOARD:U2\|N\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "KEYBOARD:U2\|FN~27 " "Info: Detected gated clock \"KEYBOARD:U2\|FN~27\" as buffer" {  } { { "KEYBOARD.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYBOARD.VHD" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KEYBOARD:U2\|FN~27" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:U1\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] " "Info: Detected ripple clock \"counter:U1\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:U1\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_40M register CONTROLER:U3\|ACC\[6\] register CONTROLER:U3\|QA 64.1 MHz 15.6 ns Internal " "Info: Clock \"CLK_40M\" has Internal fmax of 64.1 MHz between source register \"CONTROLER:U3\|ACC\[6\]\" and destination register \"CONTROLER:U3\|QA\" (period= 15.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.600 ns + Longest register register " "Info: + Longest register to register delay is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CONTROLER:U3\|ACC\[6\] 1 REG LC5_A30 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A30; Fanout = 6; REG Node = 'CONTROLER:U3\|ACC\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "" { CONTROLER:U3|ACC[6] } "NODE_NAME" } "" } } { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.000 ns) 2.000 ns CONTROLER:U3\|QA~337 2 COMB LC3_A29 1 " "Info: 2: + IC(1.000 ns) + CELL(1.000 ns) = 2.000 ns; Loc. = LC3_A29; Fanout = 1; COMB Node = 'CONTROLER:U3\|QA~337'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "2.000 ns" { CONTROLER:U3|ACC[6] CONTROLER:U3|QA~337 } "NODE_NAME" } "" } } { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 3.600 ns CONTROLER:U3\|QA~315 3 COMB LC4_A29 1 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 3.600 ns; Loc. = LC4_A29; Fanout = 1; COMB Node = 'CONTROLER:U3\|QA~315'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "1.600 ns" { CONTROLER:U3|QA~337 CONTROLER:U3|QA~315 } "NODE_NAME" } "" } } { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 6.400 ns CONTROLER:U3\|QA~278 4 COMB LC4_A36 1 " "Info: 4: + IC(1.100 ns) + CELL(1.700 ns) = 6.400 ns; Loc. = LC4_A36; Fanout = 1; COMB Node = 'CONTROLER:U3\|QA~278'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "2.800 ns" { CONTROLER:U3|QA~315 CONTROLER:U3|QA~278 } "NODE_NAME" } "" } } { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 8.300 ns CONTROLER:U3\|QA~281 5 COMB LC6_A36 2 " "Info: 5: + IC(0.300 ns) + CELL(1.600 ns) = 8.300 ns; Loc. = LC6_A36; Fanout = 2; COMB Node = 'CONTROLER:U3\|QA~281'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "1.900 ns" { CONTROLER:U3|QA~278 CONTROLER:U3|QA~281 } "NODE_NAME" } "" } } { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 9.600 ns CONTROLER:U3\|QA 6 REG LC2_A36 2 " "Info: 6: + IC(0.300 ns) + CELL(1.000 ns) = 9.600 ns; Loc. = LC2_A36; Fanout = 2; REG Node = 'CONTROLER:U3\|QA'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "1.300 ns" { CONTROLER:U3|QA~281 CONTROLER:U3|QA } "NODE_NAME" } "" } } { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns ( 71.88 % ) " "Info: Total cell delay = 6.900 ns ( 71.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 28.13 % ) " "Info: Total interconnect delay = 2.700 ns ( 28.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "9.600 ns" { CONTROLER:U3|ACC[6] CONTROLER:U3|QA~337 CONTROLER:U3|QA~315 CONTROLER:U3|QA~278 CONTROLER:U3|QA~281 CONTROLER:U3|QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.600 ns" { CONTROLER:U3|ACC[6] CONTROLER:U3|QA~337 CONTROLER:U3|QA~315 CONTROLER:U3|QA~278 CONTROLER:U3|QA~281 CONTROLER:U3|QA } { 0.000ns 1.000ns 0.000ns 1.100ns 0.300ns 0.300ns } { 0.000ns 1.000ns 1.600ns 1.700ns 1.600ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.900 ns - Smallest " "Info: - Smallest clock skew is -4.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40M destination 6.700 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_40M\" to destination register is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK_40M 1 CLK PIN_55 23 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 23; CLK Node = 'CLK_40M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "" { CLK_40M } "NODE_NAME" } "" } } { "KEYLOCK.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYLOCK.VHD" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns counter:U1\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] 2 REG LC1_A24 50 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_A24; Fanout = 50; REG Node = 'counter:U1\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "0.900 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(0.000 ns) 6.700 ns CONTROLER:U3\|QA 3 REG LC2_A36 2 " "Info: 3: + IC(3.800 ns) + CELL(0.000 ns) = 6.700 ns; Loc. = LC2_A36; Fanout = 2; REG Node = 'CONTROLER:U3\|QA'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "3.800 ns" { counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] CONTROLER:U3|QA } "NODE_NAME" } "" } } { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 37.31 % ) " "Info: Total cell delay = 2.500 ns ( 37.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 62.69 % ) " "Info: Total interconnect delay = 4.200 ns ( 62.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "6.700 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] CONTROLER:U3|QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { CLK_40M CLK_40M~out counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] CONTROLER:U3|QA } { 0.000ns 0.000ns 0.400ns 3.800ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40M source 11.600 ns - Longest register " "Info: - Longest clock path from clock \"CLK_40M\" to source register is 11.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK_40M 1 CLK PIN_55 23 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 23; CLK Node = 'CLK_40M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "" { CLK_40M } "NODE_NAME" } "" } } { "KEYLOCK.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYLOCK.VHD" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns counter:U1\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\] 2 REG LC1_A24 50 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_A24; Fanout = 50; REG Node = 'counter:U1\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "0.900 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(0.500 ns) 7.200 ns KEYBOARD:U2\|N\[3\] 3 REG LC8_A24 2 " "Info: 3: + IC(3.800 ns) + CELL(0.500 ns) = 7.200 ns; Loc. = LC8_A24; Fanout = 2; REG Node = 'KEYBOARD:U2\|N\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "4.300 ns" { counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|N[3] } "NODE_NAME" } "" } } { "KEYBOARD.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYBOARD.VHD" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.700 ns) 10.300 ns KEYBOARD:U2\|FN~27 4 COMB LC2_A32 19 " "Info: 4: + IC(1.400 ns) + CELL(1.700 ns) = 10.300 ns; Loc. = LC2_A32; Fanout = 19; COMB Node = 'KEYBOARD:U2\|FN~27'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "3.100 ns" { KEYBOARD:U2|N[3] KEYBOARD:U2|FN~27 } "NODE_NAME" } "" } } { "KEYBOARD.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/KEYBOARD.VHD" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 11.600 ns CONTROLER:U3\|ACC\[6\] 5 REG LC5_A30 6 " "Info: 5: + IC(1.300 ns) + CELL(0.000 ns) = 11.600 ns; Loc. = LC5_A30; Fanout = 6; REG Node = 'CONTROLER:U3\|ACC\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "1.300 ns" { KEYBOARD:U2|FN~27 CONTROLER:U3|ACC[6] } "NODE_NAME" } "" } } { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns ( 40.52 % ) " "Info: Total cell delay = 4.700 ns ( 40.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns ( 59.48 % ) " "Info: Total interconnect delay = 6.900 ns ( 59.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "11.600 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|N[3] KEYBOARD:U2|FN~27 CONTROLER:U3|ACC[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.600 ns" { CLK_40M CLK_40M~out counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|N[3] KEYBOARD:U2|FN~27 CONTROLER:U3|ACC[6] } { 0.000ns 0.000ns 0.400ns 3.800ns 1.400ns 1.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 1.700ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "6.700 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] CONTROLER:U3|QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { CLK_40M CLK_40M~out counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] CONTROLER:U3|QA } { 0.000ns 0.000ns 0.400ns 3.800ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "11.600 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|N[3] KEYBOARD:U2|FN~27 CONTROLER:U3|ACC[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.600 ns" { CLK_40M CLK_40M~out counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|N[3] KEYBOARD:U2|FN~27 CONTROLER:U3|ACC[6] } { 0.000ns 0.000ns 0.400ns 3.800ns 1.400ns 1.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 1.700ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "CONTROLER.VHD" "" { Text "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/CONTROLER.VHD" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "9.600 ns" { CONTROLER:U3|ACC[6] CONTROLER:U3|QA~337 CONTROLER:U3|QA~315 CONTROLER:U3|QA~278 CONTROLER:U3|QA~281 CONTROLER:U3|QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.600 ns" { CONTROLER:U3|ACC[6] CONTROLER:U3|QA~337 CONTROLER:U3|QA~315 CONTROLER:U3|QA~278 CONTROLER:U3|QA~281 CONTROLER:U3|QA } { 0.000ns 1.000ns 0.000ns 1.100ns 0.300ns 0.300ns } { 0.000ns 1.000ns 1.600ns 1.700ns 1.600ns 1.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "6.700 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] CONTROLER:U3|QA } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { CLK_40M CLK_40M~out counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] CONTROLER:U3|QA } { 0.000ns 0.000ns 0.400ns 3.800ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "KEYLOCK" "UNKNOWN" "V1" "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/db/KEYLOCK.quartus_db" { Floorplan "D:/lock/LOCK/KEYLOCK(少键版)/KEYLOCK/" "" "11.600 ns" { CLK_40M counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|N[3] KEYBOARD:U2|FN~27 CONTROLER:U3|ACC[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.600 ns" { CLK_40M CLK_40M~out counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] KEYBOARD:U2|N[3] KEYBOARD:U2|FN~27 CONTROLER:U3|ACC[6] } { 0.000ns 0.000ns 0.400ns 3.800ns 1.400ns 1.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 1.700ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK_40M 17 " "Warning: Circuit may not operate. Detected 17 non-operational path(s) clocked by clock \"CLK_40M\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}