keyboard.vhd

时间以60分种为一个周期 电子钟的格式为：XX XX XX

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_ARITH.ALL ; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; 
LIBRARY altera; 
USE altera.maxplus2.ALL;
ENTITY KEYBOARD IS
PORT(CLK:IN STD_LOGIC;  --用于译码和消抖的时钟信号 
     CLK_KEYBOARD:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
     KEY_IN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); --按键位置
     KEY_L,KEY_UNL:IN STD_LOGIC;  --上锁和解锁信号
     BACK:IN STD_LOGIC;   --退格信号
     FN:OUT STD_LOGIC;
     CLEAR:OUT STD_LOGIC;  --内部产生的清零信号
     N:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY KEYBOARD;
ARCHITECTURE ART OF KEYBOARD IS
 component debouncing 
  port( d_in : IN STD_LOGIC ; 
        clk : IN STD_LOGIC ; 
        d_out : OUT STD_LOGIC );
 end component ; --消抖模块的例化
SIGNAL C:STD_LOGIC_VECTOR(3 DOWNTO 0);--消抖结果寄存
SIGNAL FF:STD_LOGIC;  --用于内部产生清零信号
begin 
debounce : block –对扫描输入逐位消抖
BEGIN
U1: debouncing PORT MAP ( 
d_in => KEY_IN(0) , 
d_out => C(0) , 
clk => CLK 
); 

U2: debouncing PORT MAP ( 
d_in => KEY_IN(1) , 
d_out => C(1) , 
clk => CLK 
); 

U3: debouncing PORT MAP ( 
d_in => KEY_IN(2) , 
d_out => C(2) , 
clk => CLK 
); 
U4: debouncing PORT MAP ( 
d_in => KEY_IN(3) , 
d_out => C(3) , 
clk => CLK 
); 
END block debounce ; 
--****************************************************** 
--key_decoder 
key_decoder : block 
signal Z : std_logic_VECTOR(5 downto 0) ; --按键位置 
SIGNAL R1, R0 : STD_LOGIC ; 
begin 
PROCESS(clk,CLK_KEYBOARD,C) 
begin 
Z <= CLK_KEYBOARD & C ; 
IF CLK'EVENT AND CLK = '1' THEN 
case Z is 
when "000111" => N <= "0000" ;--0 
when "001011" => N <= "0001" ;--1 
when "001101" => N <= "0010" ;--2 
when "001110" => N <= "0011" ;--3 
when "010111" => N <= "0100" ;--4 
when "011011" => N <= "0101" ;--5 
when "011101" => N <= "0110" ;--6 
when "011110" => N <= "0111" ;--7 
when "100111" => N <= "1000" ;--8 
when "101011" => N <= "1001" ;--9 
when "101101" => N <= "1010" ;--a 
when "101110" => N <= "1011" ;--b 
when "110111" => N <= "1100" ;--c
when "111011" => N <= "1101" ;--d
when "111101" => N <= "1110" ;--e
when others => N <= "1111" ;   --对按键的译码
end case ; 
END IF ; 
end process ;
 
FN <= NOT ( N(3) AND N(2) AND N(1) AND N(0) ) ; 
FF <= KEY_L OR KEY_UNL; 
--To generate clear signal for ACC 
PROCESS (CLK,R1,R0) 
BEGIN 
IF CLK'EVENT AND CLK = '1' THEN 
R1 <= R0 ; R0 <= FF ; 
END IF ; 
CLEAR <= R1 AND NOT R0 ;--产生清零信号
END PROCESS ; 
end block key_decoder ;  
END ARCHITECTURE ART;