controler.vhd

时间以60分种为一个周期 电子钟的格式为：XX XX XX

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_ARITH.ALL ; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; 

ENTITY CONTROLER IS
PORT(CLK:IN STD_LOGIC;
     FN:IN STD_LOGIC;  --输入了密码，当作计数和寄存的激活信号
     KEY_L,KEY_UNL:IN STD_LOGIC; --上锁/解锁
     BACK:IN STD_LOGIC;--退格
     N:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--输入密码值
     CLK_DISPLAY: IN STD_LOGIC_VECTOR(1 DOWNTO 0);--数码管显示信号，和DB输出同步
     CLEAR:IN STD_LOGIC;--清零
     ENLOCK:OUT STD_LOGIC;--上锁解锁状态输出
     DB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));--待显示的密码值
END ENTITY CONTROLER;
ARCHITECTURE ART OF CONTROLER IS
SIGNAL NC:STD_LOGIC_VECTOR(2 DOWNTO 0);--计数信号
SIGNAL ACC,REG:STD_LOGIC_VECTOR(15 DOWNTO 0);
--内部寄存器存储密码制为BCD形式
SIGNAL QA,QB:STD_LOGIC; --产生解锁和上锁的状态控制
SIGNAL RST : STD_LOGIC; --复位信号
BEGIN

PROCESS(CLK,FN,RST,BACK) 
BEGIN 

IF RST = '1' THEN  --复位
ACC <= "0000000000000000" ; --CLEAR INPUT 
NC <= "000" ; 

ELSIF BACK ='1' THEN  --退格
  ACC <= "0000" & ACC(15 DOWNTO 4);
  NC <= NC-1;
ELSE
 IF FN'EVENT AND FN = '1' THEN 

 IF NC <4 THEN 
 
 ACC <= ACC(11 DOWNTO 0) & N ; 
 NC <= NC + 1 ; --对密码个数计数
 END IF ; 
END IF ; 
END IF ; 
END PROCESS ; 

RST <= CLEAR ; 
--********************************************* 
LOCK_PROCESS : BLOCK 
BEGIN 
PROCESS(CLK,KEY_L,KEY_UNL) 
BEGIN 
IF (CLK'EVENT AND CLK = '1') THEN 
IF NC = 4 THEN 
IF KEY_L = '1' THEN --上锁
REG <= ACC ; 
QA <= '1' ; QB <= '0';                    
ELSIF KEY_UNL = '1' THEN  --解锁
  IF (REG = ACC) THEN --CHECK PIN CODE 
      QB <= '1' ; QA<= '0'; 
  ELSIF  ACC = "1000011000001001" THEN
      QB <= '1' ; QA<= '0';                   
  END IF;
                  --设置8609为万用密码 
END IF ; 
END IF; 
END IF ;
END PROCESS ; 
END BLOCK LOCK_PROCESS ; 

ENLOCK <= QA AND NOT QB ; 
--********************************************** 
MULTIPLEXER : BLOCK 
BEGIN 
--实现将寄存的16位BCD码分时输出
DB <= ACC(15 DOWNTO 12) WHEN CLK_DISPLAY = 0 ELSE 
ACC(11 DOWNTO 8) WHEN CLK_DISPLAY = 1 ELSE 
ACC(7 DOWNTO 4) WHEN CLK_DISPLAY = 2 ELSE 
ACC(3 DOWNTO 0) WHEN CLK_DISPLAY = 3 ELSE 
"1111" ; 
End Block MULTIPLEXER ; 
END ARCHITECTURE ART;