display.vhd

时间以60分种为一个周期 电子钟的格式为：XX XX XX

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_ARITH.ALL ; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; 
ENTITY DISPLAY IS
PORT(DB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--密码值BCD码
     CLK_DISPLAY: IN STD_LOGIC_VECTOR(1 DOWNTO 0);--输出扫描
     SEGOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);动态选中数码管
     SELOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));--七段译码输出
END ENTITY DISPLAY;
ARCHITECTURE ART OF DISPLAY IS
BEGIN   --数码管的点亮序列
 SELOUT<="1000" WHEN CLK_DISPLAY=0 ELSE
         "0100" WHEN CLK_DISPLAY=1 ELSE
         "0010" WHEN CLK_DISPLAY=2 ELSE 
         "0001";

     --gfedcba BCD到七段数码管的译码输出
SEGOUT <=  "0111111" WHEN DB = 0 ELSE 
"0000110" WHEN DB = 1 ELSE 
"1011011" WHEN DB = 2 ELSE 
"1001111" WHEN DB = 3 ELSE 
"1100110" WHEN DB = 4 ELSE 
"1101101" WHEN DB = 5 ELSE 
"1111101" WHEN DB = 6 ELSE 
"0000111" WHEN DB = 7 ELSE 
"1111111" WHEN DB = 8 ELSE 
"1101111" WHEN DB = 9 ELSE 
"1110111" WHEN DB = x"a" ELSE 
"1111100" WHEN DB = x"b" ELSE 
"0111001" WHEN DB = x"c" ELSE 
"1011110" WHEN DB = x"d" ELSE 
"1111001" WHEN DB = x"e" ELSE
"1110001" WHEN DB = x"f" ELSE  
"1111111"; 
End ARCHITECTURE ART;