keylock.fit.eqn

时间以60分种为一个周期 电子钟的格式为：XX XX XX

--operation mode is normal

H4_d0_lut_out = !H4_dff2;
H4_d0 = DFFEA(H4_d0_lut_out, GLOBAL(G1_q[15]), , , , , );

--H4L2Q is KEYBOARD:U2|debouncing:\debounce:U4|d0~1 at LC1_A25
--operation mode is normal

H4L2Q = H4_d0;


--H4L5 is KEYBOARD:U2|debouncing:\debounce:U4|d_out~0 at LC8_A23
--operation mode is normal

H4L5 = !H4_d0 & H4_d1;

--H4L6 is KEYBOARD:U2|debouncing:\debounce:U4|d_out~8 at LC8_A23
--operation mode is normal

H4L6 = !H4_d0 & H4_d1;


--C1L9 is KEYBOARD:U2|Mux~39 at LC1_A23
--operation mode is normal

C1L9 = H4L5 & !H3L5 & !H2L5 & !H1L5 # !H4L5 & (H3L5 & !H2L5 & !H1L5 # !H3L5 & (H2L5 $ H1L5));

--C1L10 is KEYBOARD:U2|Mux~42 at LC1_A23
--operation mode is normal

C1L10 = H4L5 & !H3L5 & !H2L5 & !H1L5 # !H4L5 & (H3L5 & !H2L5 & !H1L5 # !H3L5 & (H2L5 $ H1L5));


--D1L38 is CONTROLER:U3|add~43 at LC6_A28
--operation mode is normal

D1L38 = D1_NC[2] $ (!D1_NC[0] & !D1_NC[1]);

--D1L40 is CONTROLER:U3|add~46 at LC6_A28
--operation mode is normal

D1L40 = D1_NC[2] $ (!D1_NC[0] & !D1_NC[1]);


--G1_q[17] is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[17] at LC3_A24
--operation mode is up_dn_cntr

G1_q[17]_lut_out = G1_q[17] $ G1L35;
G1_q[17] = DFFEA(G1_q[17]_lut_out, GLOBAL(CLK_40M), , , , , );

--G1L81Q is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[17]~8 at LC3_A24
--operation mode is up_dn_cntr

G1L81Q = G1_q[17];

--G1L37 is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[17]~COUT at LC3_A24
--operation mode is up_dn_cntr

G1L37 = CARRY(G1_q[17] & (G1L35));


--D1L39 is CONTROLER:U3|add~44 at LC7_A28
--operation mode is normal

D1L39 = D1_NC[0] $ !D1_NC[1];

--D1L41 is CONTROLER:U3|add~47 at LC7_A28
--operation mode is normal

D1L41 = D1_NC[0] $ !D1_NC[1];


--G1_q[11] is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[11] at LC5_A22
--operation mode is up_dn_cntr

G1_q[11]_lut_out = G1_q[11] $ G1L23;
G1_q[11] = DFFEA(G1_q[11]_lut_out, GLOBAL(CLK_40M), , , , , );

--G1L69Q is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[11]~9 at LC5_A22
--operation mode is up_dn_cntr

G1L69Q = G1_q[11];

--G1L25 is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT at LC5_A22
--operation mode is up_dn_cntr

G1L25 = CARRY(G1_q[11] & (G1L23));


--H1_dff2 is KEYBOARD:U2|debouncing:\debounce:U1|dff2 at LC2_A26
--operation mode is normal

H1_dff2_lut_out = VCC;
H1_dff2 = DFFEA(H1_dff2_lut_out, GLOBAL(G1_q[15]), H1_dff1, , , , );

--H1L10Q is KEYBOARD:U2|debouncing:\debounce:U1|dff2~1 at LC2_A26
--operation mode is normal

H1L10Q = H1_dff2;


--H2_dff2 is KEYBOARD:U2|debouncing:\debounce:U2|dff2 at LC4_A15
--operation mode is normal

H2_dff2_lut_out = VCC;
H2_dff2 = DFFEA(H2_dff2_lut_out, GLOBAL(G1_q[15]), H2_dff1, , , , );

--H2L10Q is KEYBOARD:U2|debouncing:\debounce:U2|dff2~1 at LC4_A15
--operation mode is normal

H2L10Q = H2_dff2;


--H3_dff2 is KEYBOARD:U2|debouncing:\debounce:U3|dff2 at LC4_A27
--operation mode is normal

H3_dff2_lut_out = VCC;
H3_dff2 = DFFEA(H3_dff2_lut_out, GLOBAL(G1_q[15]), H3_dff1, , , , );

--H3L10Q is KEYBOARD:U2|debouncing:\debounce:U3|dff2~1 at LC4_A27
--operation mode is normal

H3L10Q = H3_dff2;


--H4_dff2 is KEYBOARD:U2|debouncing:\debounce:U4|dff2 at LC2_A25
--operation mode is normal

H4_dff2_lut_out = VCC;
H4_dff2 = DFFEA(H4_dff2_lut_out, GLOBAL(G1_q[15]), H4_dff1, , , , );

--H4L10Q is KEYBOARD:U2|debouncing:\debounce:U4|dff2~1 at LC2_A25
--operation mode is normal

H4L10Q = H4_dff2;


--G1_q[16] is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[16] at LC2_A24
--operation mode is up_dn_cntr

G1_q[16]_lut_out = G1_q[16] $ G1L33;
G1_q[16] = DFFEA(G1_q[16]_lut_out, GLOBAL(CLK_40M), , , , , );

--G1L79Q is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[16]~10 at LC2_A24
--operation mode is up_dn_cntr

G1L79Q = G1_q[16];

--G1L35 is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT at LC2_A24
--operation mode is up_dn_cntr

G1L35 = CARRY(G1_q[16] & (G1L33));


--D1_REG[8] is CONTROLER:U3|REG[8] at LC2_A35
--operation mode is normal

D1_REG[8]_lut_out = D1_ACC[8];
D1_REG[8] = DFFEA(D1_REG[8]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L126Q is CONTROLER:U3|REG[8]~41 at LC2_A35
--operation mode is normal

D1L126Q = D1_REG[8];


--D1_REG[9] is CONTROLER:U3|REG[9] at LC3_A35
--operation mode is normal

D1_REG[9]_lut_out = D1_ACC[9];
D1_REG[9] = DFFEA(D1_REG[9]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L128Q is CONTROLER:U3|REG[9]~42 at LC3_A35
--operation mode is normal

D1L128Q = D1_REG[9];


--D1L71 is CONTROLER:U3|QA~300 at LC7_A35
--operation mode is normal

D1L71 = D1_REG[9] & D1_ACC[9] & (D1_REG[8] $ !D1_ACC[8]) # !D1_REG[9] & !D1_ACC[9] & (D1_REG[8] $ !D1_ACC[8]);

--D1L86 is CONTROLER:U3|QA~327 at LC7_A35
--operation mode is normal

D1L86 = D1_REG[9] & D1_ACC[9] & (D1_REG[8] $ !D1_ACC[8]) # !D1_REG[9] & !D1_ACC[9] & (D1_REG[8] $ !D1_ACC[8]);

--D1L87 is CONTROLER:U3|QA~328 at LC7_A35
--operation mode is normal

D1L87 = D1_REG[9] & D1_ACC[9] & (D1_REG[8] $ !D1_ACC[8]) # !D1_REG[9] & !D1_ACC[9] & (D1_REG[8] $ !D1_ACC[8]);


--D1_REG[1] is CONTROLER:U3|REG[1] at LC4_A35
--operation mode is normal

D1_REG[1]_lut_out = D1_ACC[1];
D1_REG[1] = DFFEA(D1_REG[1]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L112Q is CONTROLER:U3|REG[1]~43 at LC4_A35
--operation mode is normal

D1L112Q = D1_REG[1];


--D1_REG[4] is CONTROLER:U3|REG[4] at LC5_A35
--operation mode is normal

D1_REG[4]_lut_out = D1_ACC[4];
D1_REG[4] = DFFEA(D1_REG[4]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L118Q is CONTROLER:U3|REG[4]~44 at LC5_A35
--operation mode is normal

D1L118Q = D1_REG[4];


--D1L77 is CONTROLER:U3|QA~312 at LC8_A35
--operation mode is normal

D1L77 = (D1_REG[4] & D1_ACC[4] & (D1_REG[1] $ !D1_ACC[1]) # !D1_REG[4] & !D1_ACC[4] & (D1_REG[1] $ !D1_ACC[1])) & CASCADE(D1L87);

--D1L88 is CONTROLER:U3|QA~329 at LC8_A35
--operation mode is normal

D1L88 = (D1_REG[4] & D1_ACC[4] & (D1_REG[1] $ !D1_ACC[1]) # !D1_REG[4] & !D1_ACC[4] & (D1_REG[1] $ !D1_ACC[1])) & CASCADE(D1L87);


--D1_REG[10] is CONTROLER:U3|REG[10] at LC3_A33
--operation mode is normal

D1_REG[10]_lut_out = D1_ACC[10];
D1_REG[10] = DFFEA(D1_REG[10]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L130Q is CONTROLER:U3|REG[10]~45 at LC3_A33
--operation mode is normal

D1L130Q = D1_REG[10];


--D1_REG[11] is CONTROLER:U3|REG[11] at LC4_A33
--operation mode is normal

D1_REG[11]_lut_out = D1_ACC[11];
D1_REG[11] = DFFEA(D1_REG[11]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L132Q is CONTROLER:U3|REG[11]~46 at LC4_A33
--operation mode is normal

D1L132Q = D1_REG[11];


--D1L72 is CONTROLER:U3|QA~302 at LC1_A33
--operation mode is normal

D1L72 = D1_REG[11] & D1_ACC[11] & (D1_REG[10] $ !D1_ACC[10]) # !D1_REG[11] & !D1_ACC[11] & (D1_REG[10] $ !D1_ACC[10]);

--D1L89 is CONTROLER:U3|QA~330 at LC1_A33
--operation mode is normal

D1L89 = D1_REG[11] & D1_ACC[11] & (D1_REG[10] $ !D1_ACC[10]) # !D1_REG[11] & !D1_ACC[11] & (D1_REG[10] $ !D1_ACC[10]);

--D1L90 is CONTROLER:U3|QA~331 at LC1_A33
--operation mode is normal

D1L90 = D1_REG[11] & D1_ACC[11] & (D1_REG[10] $ !D1_ACC[10]) # !D1_REG[11] & !D1_ACC[11] & (D1_REG[10] $ !D1_ACC[10]);


--D1_REG[0] is CONTROLER:U3|REG[0] at LC5_A33
--operation mode is normal

D1_REG[0]_lut_out = D1_ACC[0];
D1_REG[0] = DFFEA(D1_REG[0]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L109Q is CONTROLER:U3|REG[0]~47 at LC5_A33
--operation mode is normal

D1L109Q = D1_REG[0];


--D1_REG[2] is CONTROLER:U3|REG[2] at LC6_A33
--operation mode is normal

D1_REG[2]_lut_out = D1_ACC[2];
D1_REG[2] = DFFEA(D1_REG[2]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L114Q is CONTROLER:U3|REG[2]~48 at LC6_A33
--operation mode is normal

D1L114Q = D1_REG[2];


--D1L78 is CONTROLER:U3|QA~313 at LC2_A33
--operation mode is normal

D1L78 = (D1_REG[2] & D1_ACC[2] & (D1_REG[0] $ !D1_ACC[0]) # !D1_REG[2] & !D1_ACC[2] & (D1_REG[0] $ !D1_ACC[0])) & CASCADE(D1L90);

--D1L91 is CONTROLER:U3|QA~332 at LC2_A33
--operation mode is normal

D1L91 = (D1_REG[2] & D1_ACC[2] & (D1_REG[0] $ !D1_ACC[0]) # !D1_REG[2] & !D1_ACC[2] & (D1_REG[0] $ !D1_ACC[0])) & CASCADE(D1L90);


--D1_REG[15] is CONTROLER:U3|REG[15] at LC5_A32
--operation mode is normal

D1_REG[15]_lut_out = D1_ACC[15];
D1_REG[15] = DFFEA(D1_REG[15]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L140Q is CONTROLER:U3|REG[15]~49 at LC5_A32
--operation mode is normal

D1L140Q = D1_REG[15];


--D1_REG[3] is CONTROLER:U3|REG[3] at LC6_A32
--operation mode is normal

D1_REG[3]_lut_out = D1_ACC[3];
D1_REG[3] = DFFEA(D1_REG[3]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L116Q is CONTROLER:U3|REG[3]~50 at LC6_A32
--operation mode is normal

D1L116Q = D1_REG[3];


--D1L73 is CONTROLER:U3|QA~304 at LC3_A32
--operation mode is normal

D1L73 = D1_REG[3] & D1_ACC[3] & (D1_REG[15] $ !D1_ACC[15]) # !D1_REG[3] & !D1_ACC[3] & (D1_REG[15] $ !D1_ACC[15]);

--D1L92 is CONTROLER:U3|QA~333 at LC3_A32
--operation mode is normal

D1L92 = D1_REG[3] & D1_ACC[3] & (D1_REG[15] $ !D1_ACC[15]) # !D1_REG[3] & !D1_ACC[3] & (D1_REG[15] $ !D1_ACC[15]);

--D1L93 is CONTROLER:U3|QA~334 at LC3_A32
--operation mode is normal

D1L93 = D1_REG[3] & D1_ACC[3] & (D1_REG[15] $ !D1_ACC[15]) # !D1_REG[3] & !D1_ACC[3] & (D1_REG[15] $ !D1_ACC[15]);


--D1_REG[5] is CONTROLER:U3|REG[5] at LC7_A32
--operation mode is normal

D1_REG[5]_lut_out = D1_ACC[5];
D1_REG[5] = DFFEA(D1_REG[5]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L120Q is CONTROLER:U3|REG[5]~51 at LC7_A32
--operation mode is normal

D1L120Q = D1_REG[5];


--D1_REG[12] is CONTROLER:U3|REG[12] at LC8_A32
--operation mode is normal

D1_REG[12]_lut_out = D1_ACC[12];
D1_REG[12] = DFFEA(D1_REG[12]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L134Q is CONTROLER:U3|REG[12]~52 at LC8_A32
--operation mode is normal

D1L134Q = D1_REG[12];


--D1L79 is CONTROLER:U3|QA~314 at LC4_A32
--operation mode is normal

D1L79 = (D1_REG[12] & D1_ACC[12] & (D1_REG[5] $ !D1_ACC[5]) # !D1_REG[12] & !D1_ACC[12] & (D1_REG[5] $ !D1_ACC[5])) & CASCADE(D1L93);

--D1L94 is CONTROLER:U3|QA~335 at LC4_A32
--operation mode is normal

D1L94 = (D1_REG[12] & D1_ACC[12] & (D1_REG[5] $ !D1_ACC[5]) # !D1_REG[12] & !D1_ACC[12] & (D1_REG[5] $ !D1_ACC[5])) & CASCADE(D1L93);


--D1_REG[6] is CONTROLER:U3|REG[6] at LC1_A29
--operation mode is normal

D1_REG[6]_lut_out = D1_ACC[6];
D1_REG[6] = DFFEA(D1_REG[6]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L122Q is CONTROLER:U3|REG[6]~53 at LC1_A29
--operation mode is normal

D1L122Q = D1_REG[6];


--D1_REG[14] is CONTROLER:U3|REG[14] at LC2_A29
--operation mode is normal

D1_REG[14]_lut_out = D1_ACC[14];
D1_REG[14] = DFFEA(D1_REG[14]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L138Q is CONTROLER:U3|REG[14]~54 at LC2_A29
--operation mode is normal

D1L138Q = D1_REG[14];


--D1L74 is CONTROLER:U3|QA~306 at LC3_A29
--operation mode is normal

D1L74 = D1_REG[14] & D1_ACC[14] & (D1_REG[6] $ !D1_ACC[6]) # !D1_REG[14] & !D1_ACC[14] & (D1_REG[6] $ !D1_ACC[6]);

--D1L95 is CONTROLER:U3|QA~336 at LC3_A29
--operation mode is normal

D1L95 = D1_REG[14] & D1_ACC[14] & (D1_REG[6] $ !D1_ACC[6]) # !D1_REG[14] & !D1_ACC[14] & (D1_REG[6] $ !D1_ACC[6]);

--D1L96 is CONTROLER:U3|QA~337 at LC3_A29
--operation mode is normal

D1L96 = D1_REG[14] & D1_ACC[14] & (D1_REG[6] $ !D1_ACC[6]) # !D1_REG[14] & !D1_ACC[14] & (D1_REG[6] $ !D1_ACC[6]);


--D1_REG[7] is CONTROLER:U3|REG[7] at LC5_A29
--operation mode is normal

D1_REG[7]_lut_out = D1_ACC[7];
D1_REG[7] = DFFEA(D1_REG[7]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L124Q is CONTROLER:U3|REG[7]~55 at LC5_A29
--operation mode is normal

D1L124Q = D1_REG[7];


--D1_REG[13] is CONTROLER:U3|REG[13] at LC8_A29
--operation mode is normal

D1_REG[13]_lut_out = D1_ACC[13];
D1_REG[13] = DFFEA(D1_REG[13]_lut_out, GLOBAL(G1_q[15]), , , D1L108, , );

--D1L136Q is CONTROLER:U3|REG[13]~56 at LC8_A29
--operation mode is normal

D1L136Q = D1_REG[13];


--D1L80 is CONTROLER:U3|QA~315 at LC4_A29
--operation mode is normal

D1L80 = (D1_REG[13] & D1_ACC[13] & (D1_REG[7] $ !D1_ACC[7]) # !D1_REG[13] & !D1_ACC[13] & (D1_REG[7] $ !D1_ACC[7])) & CASCADE(D1L96);

--D1L97 is CONTROLER:U3|QA~338 at LC4_A29
--operation mode is normal

D1L97 = (D1_REG[13] & D1_ACC[13] & (D1_REG[7] $ !D1_ACC[7]) # !D1_REG[13] & !D1_ACC[13] & (D1_REG[7] $ !D1_ACC[7])) & CASCADE(D1L96);


--D1L75 is CONTROLER:U3|QA~308 at LC6_A30
--operation mode is normal

D1L75 = !D1_ACC[2] & !D1_ACC[14] & !D1_ACC[6] & D1_ACC[10];