keylock.fit.eqn

时间以60分种为一个周期 电子钟的格式为：XX XX XX

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--G1_q[21] is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[21] at LC7_A24
--operation mode is up_dn_cntr

G1_q[21]_lut_out = G1_q[21] $ G1L43;
G1_q[21] = DFFEA(G1_q[21]_lut_out, GLOBAL(CLK_40M), , , , , );

--G1L89Q is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[21]~0 at LC7_A24
--operation mode is up_dn_cntr

G1L89Q = G1_q[21];


--G1_q[20] is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[20] at LC6_A24
--operation mode is up_dn_cntr

G1_q[20]_lut_out = G1_q[20] $ G1L41;
G1_q[20] = DFFEA(G1_q[20]_lut_out, GLOBAL(CLK_40M), , , , , );

--G1L87Q is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[20]~1 at LC6_A24
--operation mode is up_dn_cntr

G1L87Q = G1_q[20];

--G1L43 is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[20]~COUT at LC6_A24
--operation mode is up_dn_cntr

G1L43 = CARRY(G1_q[20] & (G1L41));


--B1L1 is counter:U1|CLK_SCAN[0]~5 at LC2_F24
--operation mode is normal

B1L1 = G1_q[20] & G1_q[21];

--B1L2 is counter:U1|CLK_SCAN[0]~6 at LC2_F24
--operation mode is normal

B1L2 = G1_q[20] & G1_q[21];


--A1L16 is rtl~0 at LC2_F25
--operation mode is normal

A1L16 = !G1_q[20] & G1_q[21];

--A1L23 is rtl~47 at LC2_F25
--operation mode is normal

A1L23 = !G1_q[20] & G1_q[21];


--A1L17 is rtl~1 at LC1_F27
--operation mode is normal

A1L17 = !G1_q[21] & G1_q[20];

--A1L24 is rtl~48 at LC1_F27
--operation mode is normal

A1L24 = !G1_q[21] & G1_q[20];


--A1L18 is rtl~2 at LC1_F29
--operation mode is normal

A1L18 = G1_q[20] # G1_q[21];

--A1L25 is rtl~49 at LC1_F29
--operation mode is normal

A1L25 = G1_q[20] # G1_q[21];


--D1_QA is CONTROLER:U3|QA at LC2_A36
--operation mode is normal

D1_QA_lut_out = KEY_L # !D1L70 & D1_QA;
D1_QA = DFFEA(D1_QA_lut_out, GLOBAL(G1_q[15]), , , A1L22, , );

--D1L83Q is CONTROLER:U3|QA~324 at LC2_A36
--operation mode is normal

D1L83Q = D1_QA;


--D1_QB is CONTROLER:U3|QB at LC3_A36
--operation mode is normal

D1_QB_lut_out = !KEY_L & (D1_QB # D1L70);
D1_QB = DFFEA(D1_QB_lut_out, GLOBAL(G1_q[15]), , , A1L22, , );

--D1L105Q is CONTROLER:U3|QB~34 at LC3_A36
--operation mode is normal

D1L105Q = D1_QB;


--D1_ENLOCK is CONTROLER:U3|ENLOCK at LC5_A36
--operation mode is normal

D1_ENLOCK = !D1_QB & D1_QA;

--D1L59 is CONTROLER:U3|ENLOCK~8 at LC5_A36
--operation mode is normal

D1L59 = !D1_QB & D1_QA;


--G1_q[15] is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15] at LC1_A24
--operation mode is up_dn_cntr

G1_q[15]_lut_out = G1_q[15] $ G1L31;
G1_q[15] = DFFEA(G1_q[15]_lut_out, GLOBAL(CLK_40M), , , , , );

--G1L77Q is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[15]~2 at LC1_A24
--operation mode is up_dn_cntr

G1L77Q = G1_q[15];

--G1L33 is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT at LC1_A24
--operation mode is up_dn_cntr

G1L33 = CARRY(G1_q[15] & (G1L31));


--G1_q[14] is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[14] at LC8_A22
--operation mode is up_dn_cntr

G1_q[14]_lut_out = G1_q[14] $ G1L29;
G1_q[14] = DFFEA(G1_q[14]_lut_out, GLOBAL(CLK_40M), , , , , );

--G1L75Q is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[14]~3 at LC8_A22
--operation mode is up_dn_cntr

G1L75Q = G1_q[14];

--G1L31 is counter:U1|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT at LC8_A22
--operation mode is up_dn_cntr

G1L31 = CARRY(G1_q[14] & (G1L29));


--E1L15 is DISPLAY:U4|SELOUT[0]~21 at LC1_A17
--operation mode is normal

E1L15 = G1_q[14] & G1_q[15];

--E1L16 is DISPLAY:U4|SELOUT[0]~22 at LC1_A17
--operation mode is normal

E1L16 = G1_q[14] & G1_q[15];


--A1L19 is rtl~3 at LC2_A17
--operation mode is normal

A1L19 = !G1_q[14] & G1_q[15];

--A1L26 is rtl~50 at LC2_A17
--operation mode is normal

A1L26 = !G1_q[14] & G1_q[15];


--A1L20 is rtl~4 at LC2_A19
--operation mode is normal

A1L20 = !G1_q[15] & G1_q[14];

--A1L27 is rtl~51 at LC2_A19
--operation mode is normal

A1L27 = !G1_q[15] & G1_q[14];


--A1L21 is rtl~5 at LC2_A21
--operation mode is normal

A1L21 = G1_q[14] # G1_q[15];

--A1L28 is rtl~52 at LC2_A21
--operation mode is normal

A1L28 = G1_q[14] # G1_q[15];


--D1_ACC[11] is CONTROLER:U3|ACC[11] at LC1_A30
--operation mode is normal

D1_ACC[11]_lut_out = D1_ACC[7];
D1_ACC[11] = DFFEA(D1_ACC[11]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[15], BACK);

--D1L26Q is CONTROLER:U3|ACC[11]~48 at LC1_A30
--operation mode is normal

D1L26Q = D1_ACC[11];


--D1_ACC[7] is CONTROLER:U3|ACC[7] at LC4_A30
--operation mode is normal

D1_ACC[7]_lut_out = D1_ACC[3];
D1_ACC[7] = DFFEA(D1_ACC[7]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[11], BACK);

--D1L17Q is CONTROLER:U3|ACC[7]~49 at LC4_A30
--operation mode is normal

D1L17Q = D1_ACC[7];


--D1_ACC[15] is CONTROLER:U3|ACC[15] at LC1_A31
--operation mode is normal

D1_ACC[15]_lut_out = D1_ACC[11];
D1_ACC[15] = DFFEA(D1_ACC[15]_lut_out, C1L7, !D1L36, , D1L25, , );

--D1L35Q is CONTROLER:U3|ACC[15]~50 at LC1_A31
--operation mode is normal

D1L35Q = D1_ACC[15];


--D1L54 is CONTROLER:U3|DB[3]~32 at LC4_A31
--operation mode is normal

D1L54 = G1_q[15] & (D1_ACC[7] # G1_q[14]) # !G1_q[15] & D1_ACC[15] & (!G1_q[14]);

--D1L56 is CONTROLER:U3|DB[3]~40 at LC4_A31
--operation mode is normal

D1L56 = G1_q[15] & (D1_ACC[7] # G1_q[14]) # !G1_q[15] & D1_ACC[15] & (!G1_q[14]);


--D1_ACC[3] is CONTROLER:U3|ACC[3] at LC1_A32
--operation mode is normal

D1_ACC[3]_lut_out = C1_N[3];
D1_ACC[3] = DFFEA(D1_ACC[3]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[7], BACK);

--D1L9Q is CONTROLER:U3|ACC[3]~51 at LC1_A32
--operation mode is normal

D1L9Q = D1_ACC[3];


--D1L55 is CONTROLER:U3|DB[3]~33 at LC3_A31
--operation mode is normal

D1L55 = D1L54 & (D1_ACC[3] # !G1_q[14]) # !D1L54 & (G1_q[14] & D1_ACC[11]);

--D1L57 is CONTROLER:U3|DB[3]~41 at LC3_A31
--operation mode is normal

D1L57 = D1L54 & (D1_ACC[3] # !G1_q[14]) # !D1L54 & (G1_q[14] & D1_ACC[11]);


--D1_ACC[10] is CONTROLER:U3|ACC[10] at LC2_A30
--operation mode is normal

D1_ACC[10]_lut_out = D1_ACC[6];
D1_ACC[10] = DFFEA(D1_ACC[10]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[14], BACK);

--D1L23Q is CONTROLER:U3|ACC[10]~52 at LC2_A30
--operation mode is normal

D1L23Q = D1_ACC[10];


--D1_ACC[6] is CONTROLER:U3|ACC[6] at LC5_A30
--operation mode is normal

D1_ACC[6]_lut_out = D1_ACC[2];
D1_ACC[6] = DFFEA(D1_ACC[6]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[10], BACK);

--D1L15Q is CONTROLER:U3|ACC[6]~53 at LC5_A30
--operation mode is normal

D1L15Q = D1_ACC[6];


--D1_ACC[14] is CONTROLER:U3|ACC[14] at LC6_A29
--operation mode is normal

D1_ACC[14]_lut_out = D1_ACC[10];
D1_ACC[14] = DFFEA(D1_ACC[14]_lut_out, C1L7, !D1L36, , D1L25, , );

--D1L33Q is CONTROLER:U3|ACC[14]~54 at LC6_A29
--operation mode is normal

D1L33Q = D1_ACC[14];


--D1L50 is CONTROLER:U3|DB[2]~34 at LC5_A17
--operation mode is normal

D1L50 = G1_q[15] & (D1_ACC[6] # G1_q[14]) # !G1_q[15] & D1_ACC[14] & (!G1_q[14]);

--D1L52 is CONTROLER:U3|DB[2]~42 at LC5_A17
--operation mode is normal

D1L52 = G1_q[15] & (D1_ACC[6] # G1_q[14]) # !G1_q[15] & D1_ACC[14] & (!G1_q[14]);


--D1_ACC[2] is CONTROLER:U3|ACC[2] at LC3_A30
--operation mode is normal

D1_ACC[2]_lut_out = C1_N[2];
D1_ACC[2] = DFFEA(D1_ACC[2]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[6], BACK);

--D1L7Q is CONTROLER:U3|ACC[2]~55 at LC3_A30
--operation mode is normal

D1L7Q = D1_ACC[2];


--D1L51 is CONTROLER:U3|DB[2]~35 at LC8_A30
--operation mode is normal

D1L51 = D1L50 & (D1_ACC[2] # !G1_q[14]) # !D1L50 & (G1_q[14] & D1_ACC[10]);

--D1L53 is CONTROLER:U3|DB[2]~43 at LC8_A30
--operation mode is normal

D1L53 = D1L50 & (D1_ACC[2] # !G1_q[14]) # !D1L50 & (G1_q[14] & D1_ACC[10]);


--D1_ACC[9] is CONTROLER:U3|ACC[9] at LC7_A34
--operation mode is normal

D1_ACC[9]_lut_out = D1_ACC[5];
D1_ACC[9] = DFFEA(D1_ACC[9]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[13], BACK);

--D1L21Q is CONTROLER:U3|ACC[9]~56 at LC7_A34
--operation mode is normal

D1L21Q = D1_ACC[9];


--D1_ACC[5] is CONTROLER:U3|ACC[5] at LC6_A34
--operation mode is normal

D1_ACC[5]_lut_out = D1_ACC[1];
D1_ACC[5] = DFFEA(D1_ACC[5]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[9], BACK);

--D1L13Q is CONTROLER:U3|ACC[5]~57 at LC6_A34
--operation mode is normal

D1L13Q = D1_ACC[5];


--D1_ACC[13] is CONTROLER:U3|ACC[13] at LC7_A29
--operation mode is normal

D1_ACC[13]_lut_out = D1_ACC[9];
D1_ACC[13] = DFFEA(D1_ACC[13]_lut_out, C1L7, !D1L36, , D1L25, , );

--D1L31Q is CONTROLER:U3|ACC[13]~58 at LC7_A29
--operation mode is normal

D1L31Q = D1_ACC[13];


--D1L46 is CONTROLER:U3|DB[1]~36 at LC7_A17
--operation mode is normal

D1L46 = G1_q[15] & (D1_ACC[5] # G1_q[14]) # !G1_q[15] & D1_ACC[13] & (!G1_q[14]);

--D1L48 is CONTROLER:U3|DB[1]~44 at LC7_A17
--operation mode is normal

D1L48 = G1_q[15] & (D1_ACC[5] # G1_q[14]) # !G1_q[15] & D1_ACC[13] & (!G1_q[14]);


--D1_ACC[1] is CONTROLER:U3|ACC[1] at LC8_A34
--operation mode is normal

D1_ACC[1]_lut_out = C1_N[1];
D1_ACC[1] = DFFEA(D1_ACC[1]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[5], BACK);

--D1L5Q is CONTROLER:U3|ACC[1]~59 at LC8_A34
--operation mode is normal

D1L5Q = D1_ACC[1];


--D1L47 is CONTROLER:U3|DB[1]~37 at LC6_A17
--operation mode is normal

D1L47 = D1L46 & (D1_ACC[1] # !G1_q[14]) # !D1L46 & (G1_q[14] & D1_ACC[9]);

--D1L49 is CONTROLER:U3|DB[1]~45 at LC6_A17
--operation mode is normal

D1L49 = D1L46 & (D1_ACC[1] # !G1_q[14]) # !D1L46 & (G1_q[14] & D1_ACC[9]);


--D1_ACC[8] is CONTROLER:U3|ACC[8] at LC1_A34
--operation mode is normal

D1_ACC[8]_lut_out = D1_ACC[4];
D1_ACC[8] = DFFEA(D1_ACC[8]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[12], BACK);

--D1L19Q is CONTROLER:U3|ACC[8]~60 at LC1_A34
--operation mode is normal

D1L19Q = D1_ACC[8];


--D1_ACC[4] is CONTROLER:U3|ACC[4] at LC4_A34
--operation mode is normal

D1_ACC[4]_lut_out = D1_ACC[0];
D1_ACC[4] = DFFEA(D1_ACC[4]_lut_out, C1L7, !C1_CLEAR, , D1L25, D1_ACC[8], BACK);

--D1L11Q is CONTROLER:U3|ACC[4]~61 at LC4_A34
--operation mode is normal

D1L11Q = D1_ACC[4];


--D1_ACC[12] is CONTROLER:U3|ACC[12] at LC2_A31
--operation mode is normal

D1_ACC[12]_lut_out = D1_ACC[8];
D1_ACC[12] = DFFEA(D1_ACC[12]_lut_out, C1L7, !D1L36, , D1L25, , );

--D1L29Q is CONTROLER:U3|ACC[12]~62 at LC2_A31
--operation mode is normal

D1L29Q = D1_ACC[12];


--D1L42 is CONTROLER:U3|DB[0]~38 at LC6_A31
--operation mode is normal

D1L42 = G1_q[15] & (D1_ACC[4] # G1_q[14]) # !G1_q[15] & D1_ACC[12] & (!G1_q[14]);

--D1L44 is CONTROLER:U3|DB[0]~46 at LC6_A31
--operation mode is normal

D1L44 = G1_q[15] & (D1_ACC[4] # G1_q[14]) # !G1_q[15] & D1_ACC[12] & (!G1_q[14]);


--D1_ACC[0] is CONTROLER:U3|ACC[0] at LC5_A34
--operation mode is normal