keylock.rpp.talkback.xml

时间以60分种为一个周期 电子钟的格式为：XX XX XX

		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Configuration device</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>JTAG user code for configuration device</option>
		<setting>Ffffffff</setting>
		<default_value>Ffffffff</default_value>
	</row>
	<row>
		<option>Configuration device auto user code</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto-increment JTAG user code for multiple configuration devices</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable CONF_DONE and nSTATUS pull-ups on configuration device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Tabular Text File (.ttf) For Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Raw Binary File (.rbf) For Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Hexadecimal Output File start address</option>
		<setting>0</setting>
		<default_value>0</default_value>
	</row>
	<row>
		<option>Hexadecimal Output File count direction</option>
		<setting>Up</setting>
		<default_value>Up</default_value>
	</row>
	<row>
		<option>Release clears before tri-states</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto-restart configuration after error</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</assembler_settings>
<general_register_statistics>
	<row>
		<statistic>Total registers</statistic>
		<value>21</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Clock Enable</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Preset</statistic>
		<value>0</value>
	</row>
</general_register_statistics>
<clock_settings_summary>
	<row>
		<clock_node_name>CLK_40M</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<input_pins>
	<row>
		<name>CLK_40M</name>
		<pin__>55</pin__>
		<fan_out>21</fan_out>
		<global>yes</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>KEY_IN[0]</name>
		<pin__>56</pin__>
		<fan_out>0</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>KEY_IN[1]</name>
		<pin__>54</pin__>
		<fan_out>0</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>KEY_IN[2]</name>
		<pin__>124</pin__>
		<fan_out>0</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>KEY_IN[3]</name>
		<pin__>126</pin__>
		<fan_out>0</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
</input_pins>
<output_pins>
	<row>
		<name>KEY_SCAN[0]</name>
		<pin__>17</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>KEY_SCAN[1]</name>
		<pin__>97</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>KEY_SCAN[2]</name>
		<pin__>14</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>KEY_SCAN[3]</name>
		<pin__>12</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SELOUT[0]</name>
		<pin__>11</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SELOUT[1]</name>
		<pin__>13</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SELOUT[2]</name>
		<pin__>18</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SELOUT[3]</name>
		<pin__>96</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>FN</name>
		<pin__>112</pin__>
		<col.>4</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>FF</name>
		<pin__>95</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>ENLOCK</name>
		<pin__>47</pin__>
		<col.>25</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SEGOUT[0]</name>
		<pin__>64</pin__>
		<col.>10</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SEGOUT[1]</name>
		<pin__>59</pin__>
		<col.>16</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SEGOUT[2]</name>
		<pin__>38</pin__>
		<col.>34</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SEGOUT[3]</name>
		<pin__>69</pin__>
		<col.>6</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SEGOUT[4]</name>
		<pin__>46</pin__>
		<col.>27</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SEGOUT[5]</name>
		<pin__>113</pin__>
		<col.>5</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>SEGOUT[6]</name>
		<pin__>63</pin__>
		<col.>11</col.>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
</output_pins>
</talkback>