📄 232__.rpt
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!_LC3_B9 = _LC3_B9~NOT;
_LC3_B9~NOT = LCELL( _EQ045);
_EQ045 = _LC1_B9
# _LC4_B6
# !_LC2_B6;
-- Node name is '|SERIALOUT:2|:309'
-- Equation name is '_LC3_B6', type is buried
!_LC3_B6 = _LC3_B6~NOT;
_LC3_B6~NOT = LCELL( _EQ046);
_EQ046 = _LC1_B9
# _LC4_B6
# !_LC7_B6
# _LC5_B6;
-- Node name is '|SERIALOUT:2|:494'
-- Equation name is '_LC6_B5', type is buried
_LC6_B5 = LCELL( _EQ047);
_EQ047 = _LC4_B3 & _LC7_B10
# _LC2_B5 & _LC7_B10
# _LC5_B5 & !_LC7_B10;
-- Node name is '|SERIALOUT:2|:497'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = LCELL( _EQ048);
_EQ048 = _LC3_B5 & _LC4_B10
# _LC2_B3 & !_LC4_B10;
-- Node name is '|SERIALOUT:2|:500'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = LCELL( _EQ049);
_EQ049 = _LC1_B3 & !_LC2_B10
# _LC2_B10 & _LC3_B3;
-- Node name is '|SERIALOUT:2|:503'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = LCELL( _EQ050);
_EQ050 = _LC1_B5 & !_LC2_B10
# _LC2_B10 & _LC5_B3;
-- Node name is '|SERIALOUT:2|:507'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = LCELL( _EQ051);
_EQ051 = !_LC2_B10 & !_LC4_B10 & _LC5_B1
# _LC2_B10 & !_LC4_B10 & _LC8_B3;
-- Node name is '|SERIALOUT:2|:508'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = LCELL( _EQ052);
_EQ052 = !_LC2_B10 & _LC4_B10 & _LC6_B3
# _LC2_B10 & _LC4_B10 & _LC7_B3;
-- Node name is '|SERIALOUT:2|:621'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = LCELL( _EQ053);
_EQ053 = !_LC3_B10 & _LC4_B8 & _LC5_B8;
-- Node name is '|SERIALOUT:2|:631'
-- Equation name is '_LC3_B8', type is buried
!_LC3_B8 = _LC3_B8~NOT;
_LC3_B8~NOT = LCELL( _EQ054);
_EQ054 = !_LC5_B8
# _LC3_B10
# _LC4_B8;
-- Node name is '|SERIALOUT:2|:641'
-- Equation name is '_LC6_B8', type is buried
!_LC6_B8 = _LC6_B8~NOT;
_LC6_B8~NOT = LCELL( _EQ055);
_EQ055 = _LC5_B8
# _LC3_B10
# !_LC4_B8;
-- Node name is '|SERIALOUT:2|:651'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = LCELL( _EQ056);
_EQ056 = !_LC3_B10 & !_LC4_B8 & !_LC5_B8;
-- Node name is '|SERIALOUT:2|~656~1'
-- Equation name is '_LC8_B10', type is buried
-- synthesized logic cell
_LC8_B10 = LCELL( _EQ057);
_EQ057 = !_LC6_B8 & !_LC7_B8;
-- Node name is '|SERIALOUT:2|:682'
-- Equation name is '_LC6_B10', type is buried
_LC6_B10 = LCELL( _EQ058);
_EQ058 = !_LC3_B9 & _LC6_B8;
-- Node name is '|SERIALOUT:2|:683'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = LCELL( _EQ059);
_EQ059 = _LC3_B6 & _LC3_B8;
-- Node name is '|SERIALOUT:2|:825'
-- Equation name is '_LC7_B5', type is buried
_LC7_B5 = LCELL( _EQ060);
_EQ060 = _LC6_B5 & _LC8_B8
# _LC4_B5 & !_LC8_B8
# !_LC3_B9 & !_LC8_B8;
-- Node name is '|SERIALOUT:2|:833'
-- Equation name is '_LC8_B5', type is buried
_LC8_B5 = LCELL( _EQ061);
_EQ061 = !_LC3_B8 & !_LC6_B8 & _LC7_B5
# _LC3_B8 & _LC4_B5 & !_LC6_B8;
-- Node name is '|SERIALOUT:2|:840'
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ062);
_EQ062 = _LC1_B9 & !_LC4_B6
# _LC1_B9 & !_LC2_B6
# !_LC1_B9 & _LC2_B6 & _LC4_B6 & !_LC8_B8
# _LC1_B9 & _LC8_B8;
-- Node name is '|SERIALOUT:2|:843'
-- Equation name is '_LC7_B9', type is buried
_LC7_B9 = LCELL( _EQ063);
_EQ063 = !_LC3_B8 & _LC5_B9
# !_LC3_B6 & _LC3_B8 & _LC6_B9;
-- Node name is '|SERIALOUT:2|:846'
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ064);
_EQ064 = !_LC6_B8 & _LC7_B9
# _LC6_B9 & _LC6_B10;
-- Node name is '|SERIALOUT:2|~864~1'
-- Equation name is '_LC5_B10', type is buried
-- synthesized logic cell
_LC5_B10 = LCELL( _EQ065);
_EQ065 = !_LC3_B8 & !_LC6_B8 & _LC8_B8
# _LC7_B8;
-- Node name is '|SERIALOUT:2|~864~2'
-- Equation name is '_LC4_B9', type is buried
-- synthesized logic cell
_LC4_B9 = LCELL( _EQ066);
_EQ066 = !_LC3_B6 & _LC3_B8
# !_LC3_B8 & !_LC3_B9 & !_LC8_B8;
-- Node name is '|SERIALOUT:2|~864~3'
-- Equation name is '_LC2_B9', type is buried
-- synthesized logic cell
_LC2_B9 = LCELL( _EQ067);
_EQ067 = _LC6_B10
# _LC4_B9 & !_LC6_B8;
-- Node name is '|SERIALOUT:2|~864~4'
-- Equation name is '_LC8_B6', type is buried
-- synthesized logic cell
_LC8_B6 = LCELL( _EQ068);
_EQ068 = !_LC2_B6 & _LC4_B6
# _LC2_B6 & !_LC4_B6 & !_LC7_B8;
-- Node name is '|SERIALOUT:2|~879~1'
-- Equation name is '_LC6_B6', type is buried
-- synthesized logic cell
_LC6_B6 = LCELL( _EQ069);
_EQ069 = !_LC5_B6 & _LC7_B6
# _LC5_B6 & !_LC7_B6 & !_LC7_B8;
-- Node name is '|SERIALOUT:2|~894~1'
-- Equation name is '_LC1_B6', type is buried
-- synthesized logic cell
_LC1_B6 = LCELL( _EQ070);
_EQ070 = !_LC3_B6 & _LC3_B8
# !_LC3_B8 & !_LC8_B8
# _LC6_B8;
-- Node name is '|SERIALOUT:2|~939~1'
-- Equation name is '_LC1_B10', type is buried
-- synthesized logic cell
!_LC1_B10 = _LC1_B10~NOT;
_LC1_B10~NOT = LCELL( _EQ071);
_EQ071 = !_LC3_B8 & !_LC6_B8 & !_LC7_B8 & _LC8_B8;
Project Information f:\fpga 232\232__.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,466K
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