📄 232__.rpt
字号:
Total: 1 7 8 0 14 8 0 13 8 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 74/0
Device-Specific Information: f:\fpga 232\232__.rpt
232__
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
39 - - - -- INPUT G ^ 0 0 0 0 clk
91 - - - -- INPUT ^ 0 0 0 1 qin0
90 - - - -- INPUT ^ 0 0 0 1 qin1
40 - - - -- INPUT ^ 0 0 0 1 qin2
89 - - - -- INPUT ^ 0 0 0 1 qin3
61 - - B -- INPUT ^ 0 0 0 1 qin4
13 - - B -- INPUT ^ 0 0 0 1 qin5
15 - - B -- INPUT ^ 0 0 0 1 qin6
62 - - B -- INPUT ^ 0 0 0 1 qin7
38 - - - -- INPUT ^ 0 0 0 9 wr
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\fpga 232\232__.rpt
232__
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
64 - - B -- OUTPUT 0 1 0 0 tdempty
63 - - B -- OUTPUT 0 1 0 0 txd
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\fpga 232\232__.rpt
232__
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 02 AND2 0 2 0 1 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:87
- 5 - A 02 AND2 0 4 0 4 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:95
- 2 - A 08 AND2 0 3 0 5 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:103
- 5 - A 11 AND2 0 3 0 1 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:111
- 8 - A 11 AND2 0 4 0 2 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:115
- 3 - A 11 OR2 s 0 4 0 1 |FEN1250:1|LPM_COMPARE:156|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|comptree:sub_comptree|cmpchain:gt_cmp_end|~40~1
- 3 - A 08 AND2 s 0 4 0 1 |FEN1250:1|LPM_COMPARE:156|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|comptree:sub_comptree|cmpchain:gt_cmp_end|~40~2
- 1 - A 05 DFFE + 0 4 0 20 |FEN1250:1|:2
- 5 - A 05 DFFE + 0 1 0 2 |FEN1250:1|cnt10 (|FEN1250:1|:4)
- 3 - A 05 DFFE + 0 1 0 3 |FEN1250:1|cnt9 (|FEN1250:1|:5)
- 6 - A 11 DFFE + 0 2 0 3 |FEN1250:1|cnt8 (|FEN1250:1|:6)
- 4 - A 11 DFFE + 0 3 0 4 |FEN1250:1|cnt7 (|FEN1250:1|:7)
- 2 - A 11 DFFE + 0 2 0 6 |FEN1250:1|cnt6 (|FEN1250:1|:8)
- 4 - A 08 DFFE + 0 3 0 3 |FEN1250:1|cnt5 (|FEN1250:1|:9)
- 5 - A 08 DFFE + 0 2 0 4 |FEN1250:1|cnt4 (|FEN1250:1|:10)
- 2 - A 02 DFFE + 0 3 0 2 |FEN1250:1|cnt3 (|FEN1250:1|:11)
- 3 - A 02 DFFE + 0 3 0 3 |FEN1250:1|cnt2 (|FEN1250:1|:12)
- 6 - A 02 DFFE + 0 2 0 4 |FEN1250:1|cnt1 (|FEN1250:1|:13)
- 4 - A 02 DFFE + 0 0 0 5 |FEN1250:1|cnt0 (|FEN1250:1|:14)
- 1 - A 08 OR2 s 0 3 0 1 |FEN1250:1|~29~1
- 1 - A 11 OR2 s 0 3 0 1 |FEN1250:1|~29~2
- 1 - A 02 OR2 s 0 4 0 1 |FEN1250:1|~29~3
- 8 - A 05 OR2 ! 0 4 0 10 |FEN1250:1|:29
- 4 - A 05 OR2 0 4 0 2 |FEN1250:1|:87
- 2 - A 05 OR2 0 3 0 2 |FEN1250:1|:93
- 2 - B 06 AND2 0 2 0 4 |SERIALOUT:2|LPM_ADD_SUB:238|addcore:adder|:55
- 6 - B 09 OR2 0 3 0 2 |SERIALOUT:2|LPM_ADD_SUB:238|addcore:adder|:69
- 2 - B 08 DFFE 0 4 1 0 |SERIALOUT:2|:11
- 3 - B 10 DFFE 0 5 0 6 |SERIALOUT:2|state2 (|SERIALOUT:2|:14)
- 5 - B 08 DFFE 0 4 0 5 |SERIALOUT:2|state1 (|SERIALOUT:2|:15)
- 4 - B 08 DFFE 1 4 0 6 |SERIALOUT:2|state0 (|SERIALOUT:2|:16)
- 7 - B 03 DFFE 2 2 0 1 |SERIALOUT:2|qinbuf7 (|SERIALOUT:2|:17)
- 6 - B 03 DFFE 2 2 0 1 |SERIALOUT:2|qinbuf6 (|SERIALOUT:2|:18)
- 8 - B 03 DFFE 2 2 0 1 |SERIALOUT:2|qinbuf5 (|SERIALOUT:2|:19)
- 5 - B 01 DFFE 2 2 0 1 |SERIALOUT:2|qinbuf4 (|SERIALOUT:2|:20)
- 5 - B 03 DFFE 2 2 0 1 |SERIALOUT:2|qinbuf3 (|SERIALOUT:2|:21)
- 1 - B 05 DFFE 2 2 0 1 |SERIALOUT:2|qinbuf2 (|SERIALOUT:2|:22)
- 3 - B 03 DFFE 2 2 0 1 |SERIALOUT:2|qinbuf1 (|SERIALOUT:2|:23)
- 1 - B 03 DFFE 2 2 0 1 |SERIALOUT:2|qinbuf0 (|SERIALOUT:2|:24)
- 4 - B 05 DFFE 0 4 1 2 |SERIALOUT:2|txds (|SERIALOUT:2|:25)
- 1 - B 09 DFFE 0 3 0 4 |SERIALOUT:2|xcnt3 (|SERIALOUT:2|:26)
- 4 - B 06 DFFE 0 4 0 5 |SERIALOUT:2|xcnt2 (|SERIALOUT:2|:27)
- 7 - B 06 DFFE 0 4 0 3 |SERIALOUT:2|xcnt1 (|SERIALOUT:2|:28)
- 5 - B 06 DFFE 0 4 0 3 |SERIALOUT:2|xcnt0 (|SERIALOUT:2|:29)
- 7 - B 10 DFFE 0 4 0 1 |SERIALOUT:2|xbitcnt2 (|SERIALOUT:2|:30)
- 4 - B 10 DFFE 0 3 0 4 |SERIALOUT:2|xbitcnt1 (|SERIALOUT:2|:31)
- 2 - B 10 DFFE 0 2 0 6 |SERIALOUT:2|xbitcnt0 (|SERIALOUT:2|:32)
- 3 - B 09 OR2 ! 0 3 0 5 |SERIALOUT:2|:220
- 3 - B 06 OR2 ! 0 4 0 4 |SERIALOUT:2|:309
- 6 - B 05 OR2 0 4 0 1 |SERIALOUT:2|:494
- 5 - B 05 OR2 0 3 0 1 |SERIALOUT:2|:497
- 2 - B 03 OR2 0 3 0 1 |SERIALOUT:2|:500
- 3 - B 05 OR2 0 3 0 1 |SERIALOUT:2|:503
- 2 - B 05 OR2 0 4 0 1 |SERIALOUT:2|:507
- 4 - B 03 OR2 0 4 0 1 |SERIALOUT:2|:508
- 8 - B 08 AND2 0 3 0 7 |SERIALOUT:2|:621
- 3 - B 08 OR2 ! 0 3 0 8 |SERIALOUT:2|:631
- 6 - B 08 OR2 ! 0 3 0 8 |SERIALOUT:2|:641
- 7 - B 08 AND2 0 3 0 17 |SERIALOUT:2|:651
- 8 - B 10 AND2 s 0 2 0 1 |SERIALOUT:2|~656~1
- 6 - B 10 AND2 0 2 0 4 |SERIALOUT:2|:682
- 1 - B 08 AND2 0 2 0 1 |SERIALOUT:2|:683
- 7 - B 05 OR2 0 4 0 1 |SERIALOUT:2|:825
- 8 - B 05 OR2 0 4 0 1 |SERIALOUT:2|:833
- 5 - B 09 OR2 0 4 0 1 |SERIALOUT:2|:840
- 7 - B 09 OR2 0 4 0 1 |SERIALOUT:2|:843
- 8 - B 09 OR2 0 4 0 1 |SERIALOUT:2|:846
- 5 - B 10 OR2 s 0 4 0 3 |SERIALOUT:2|~864~1
- 4 - B 09 OR2 s 0 4 0 1 |SERIALOUT:2|~864~2
- 2 - B 09 OR2 s 0 3 0 2 |SERIALOUT:2|~864~3
- 8 - B 06 OR2 s 0 3 0 1 |SERIALOUT:2|~864~4
- 6 - B 06 OR2 s 0 3 0 1 |SERIALOUT:2|~879~1
- 1 - B 06 OR2 s 0 4 0 1 |SERIALOUT:2|~894~1
- 1 - B 10 AND2 s ! 0 4 0 3 |SERIALOUT:2|~939~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\fpga 232\232__.rpt
232__
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 13/ 96( 13%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 27/ 96( 28%) 2/ 48( 4%) 0/ 48( 0%) 4/16( 25%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\fpga 232\232__.rpt
232__
** CLOCK SIGNALS **
Type Fan-out Name
DFF 20 |FEN1250:1|:2
INPUT 12 clk
Device-Specific Information: f:\fpga 232\232__.rpt
232__
** EQUATIONS **
clk : INPUT;
qin0 : INPUT;
qin1 : INPUT;
qin2 : INPUT;
qin3 : INPUT;
qin4 : INPUT;
qin5 : INPUT;
qin6 : INPUT;
qin7 : INPUT;
wr : INPUT;
-- Node name is 'tdempty'
-- Equation name is 'tdempty', type is output
tdempty = _LC2_B8;
-- Node name is 'txd'
-- Equation name is 'txd', type is output
txd = _LC4_B5;
-- Node name is '|FEN1250:1|:14' = '|FEN1250:1|cnt0'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = DFFE(!_LC4_A2, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|FEN1250:1|:13' = '|FEN1250:1|cnt1'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC4_A2 & _LC6_A2 & !_LC8_A5
# _LC4_A2 & !_LC6_A2 & !_LC8_A5;
-- Node name is '|FEN1250:1|:12' = '|FEN1250:1|cnt2'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC3_A2 & !_LC6_A2 & !_LC8_A5
# _LC3_A2 & !_LC4_A2 & !_LC8_A5
# !_LC3_A2 & _LC4_A2 & _LC6_A2 & !_LC8_A5;
-- Node name is '|FEN1250:1|:11' = '|FEN1250:1|cnt3'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC2_A2 & !_LC3_A2 & !_LC8_A5
# _LC2_A2 & !_LC7_A2 & !_LC8_A5
# !_LC2_A2 & _LC3_A2 & _LC7_A2 & !_LC8_A5;
-- Node name is '|FEN1250:1|:10' = '|FEN1250:1|cnt4'
-- Equation name is '_LC5_A8', type is buried
_LC5_A8 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC5_A2 & _LC5_A8 & !_LC8_A5
# _LC5_A2 & !_LC5_A8 & !_LC8_A5;
-- Node name is '|FEN1250:1|:9' = '|FEN1250:1|cnt5'
-- Equation name is '_LC4_A8', type is buried
_LC4_A8 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
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