📄 232.rpt
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Synthesized logic cells: 32/ 576 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 0 0 0 0 0 8 6 38/0
B: 0 2 0 0 7 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 1 8 8 8 4 0 8 8 8 1 8 70/0
Total: 0 2 0 0 7 0 8 0 8 0 0 0 0 8 1 16 16 16 4 0 8 8 8 9 14 133/0
Device-Specific Information: f:\fpga 232\232.rpt
232
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
39 - - - -- INPUT G ^ 0 0 0 0 clk
40 - - - -- INPUT ^ 0 0 0 21 tdemptyin
38 - - - -- INPUT ^ 0 0 0 9 wrin
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\fpga 232\232.rpt
232
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
5 - - A -- OUTPUT 0 1 0 0 tdemptyout
10 - - A -- OUTPUT 0 1 0 0 txd
21 - - C -- OUTPUT 0 1 0 0 wrout
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\fpga 232\232.rpt
232
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 09 AND2 0 2 0 1 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:87
- 4 - B 09 AND2 0 4 0 4 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:95
- 2 - B 09 AND2 0 3 0 5 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:103
- 4 - B 05 AND2 0 3 0 1 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:111
- 2 - B 05 AND2 0 4 0 2 |FEN1250:1|LPM_ADD_SUB:64|addcore:adder|:115
- 5 - B 05 OR2 s 0 4 0 1 |FEN1250:1|LPM_COMPARE:156|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|comptree:sub_comptree|cmpchain:gt_cmp_end|~40~1
- 3 - B 09 AND2 s 0 4 0 1 |FEN1250:1|LPM_COMPARE:156|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|comptree:sub_comptree|cmpchain:gt_cmp_end|~40~2
- 1 - B 07 DFFE + 0 4 0 32 |FEN1250:1|:2
- 7 - B 07 DFFE + 0 1 0 2 |FEN1250:1|cnt10 (|FEN1250:1|:4)
- 5 - B 07 DFFE + 0 1 0 3 |FEN1250:1|cnt9 (|FEN1250:1|:5)
- 7 - B 05 DFFE + 0 2 0 3 |FEN1250:1|cnt8 (|FEN1250:1|:6)
- 3 - B 05 DFFE + 0 3 0 4 |FEN1250:1|cnt7 (|FEN1250:1|:7)
- 6 - B 05 DFFE + 0 2 0 6 |FEN1250:1|cnt6 (|FEN1250:1|:8)
- 6 - B 09 DFFE + 0 3 0 3 |FEN1250:1|cnt5 (|FEN1250:1|:9)
- 7 - B 09 DFFE + 0 2 0 4 |FEN1250:1|cnt4 (|FEN1250:1|:10)
- 8 - B 09 DFFE + 0 3 0 2 |FEN1250:1|cnt3 (|FEN1250:1|:11)
- 8 - B 07 DFFE + 0 3 0 3 |FEN1250:1|cnt2 (|FEN1250:1|:12)
- 2 - B 02 DFFE + 0 2 0 4 |FEN1250:1|cnt1 (|FEN1250:1|:13)
- 8 - B 02 DFFE + 0 0 0 5 |FEN1250:1|cnt0 (|FEN1250:1|:14)
- 1 - B 09 OR2 s 0 3 0 1 |FEN1250:1|~29~1
- 1 - B 05 OR2 s 0 3 0 1 |FEN1250:1|~29~2
- 3 - B 07 OR2 s 0 4 0 1 |FEN1250:1|~29~3
- 2 - B 07 OR2 ! 0 4 0 10 |FEN1250:1|:29
- 6 - B 07 OR2 0 4 0 2 |FEN1250:1|:87
- 4 - B 07 OR2 0 3 0 2 |FEN1250:1|:93
- 4 - C 22 DFFE 1 4 1 0 |SENTWORD:2|:3
- 2 - C 13 DFFE 0 5 0 1 |SENTWORD:2|:7
- 8 - C 17 DFFE 0 5 0 1 |SENTWORD:2|:9
- 7 - C 13 DFFE 0 5 0 1 |SENTWORD:2|:11
- 4 - C 13 DFFE 0 5 0 1 |SENTWORD:2|:13
- 3 - C 17 DFFE 0 5 0 1 |SENTWORD:2|:15
- 4 - C 21 DFFE 0 5 0 1 |SENTWORD:2|:17
- 3 - C 13 DFFE 0 5 0 1 |SENTWORD:2|:19
- 7 - C 22 DFFE 1 4 0 19 |SENTWORD:2|state3 (|SENTWORD:2|:22)
- 6 - C 24 DFFE 1 4 0 19 |SENTWORD:2|state2 (|SENTWORD:2|:23)
- 3 - C 15 DFFE 0 3 0 19 |SENTWORD:2|state1 (|SENTWORD:2|:24)
- 4 - C 24 DFFE 1 4 0 19 |SENTWORD:2|state0 (|SENTWORD:2|:25)
- 1 - C 13 AND2 0 4 0 4 |SENTWORD:2|:1643
- 2 - C 18 AND2 0 4 0 4 |SENTWORD:2|:1657
- 6 - C 13 AND2 0 4 0 6 |SENTWORD:2|:1671
- 8 - C 16 AND2 0 4 0 7 |SENTWORD:2|:1685
- 3 - C 18 OR2 ! 0 4 0 7 |SENTWORD:2|:1699
- 1 - C 16 OR2 ! 0 4 0 4 |SENTWORD:2|:1713
- 8 - C 18 AND2 0 4 0 7 |SENTWORD:2|:1727
- 1 - C 18 AND2 0 4 0 5 |SENTWORD:2|:1741
- 7 - C 16 AND2 0 4 0 6 |SENTWORD:2|:1755
- 6 - C 16 OR2 ! 0 4 0 4 |SENTWORD:2|:1769
- 4 - C 16 OR2 ! 0 4 0 8 |SENTWORD:2|:1783
- 3 - C 16 OR2 ! 0 4 0 4 |SENTWORD:2|:1797
- 5 - C 16 OR2 ! 0 4 0 4 |SENTWORD:2|:1811
- 2 - C 16 OR2 ! 0 4 0 4 |SENTWORD:2|:1825
- 3 - C 20 OR2 0 3 0 2 |SENTWORD:2|:1846
- 1 - C 20 OR2 s 0 4 0 1 |SENTWORD:2|~1909~1
- 8 - C 20 OR2 0 4 0 1 |SENTWORD:2|:2034
- 1 - C 17 OR2 s 0 2 0 1 |SENTWORD:2|~2041~1
- 7 - C 24 AND2 s 0 3 0 5 |SENTWORD:2|~2055~1
- 3 - C 21 OR2 s 0 2 0 1 |SENTWORD:2|~2083~1
- 3 - C 23 AND2 s 0 2 0 3 |SENTWORD:2|~2100~1
- 6 - C 20 OR2 0 4 0 1 |SENTWORD:2|:2209
- 5 - C 22 OR2 s ! 0 3 0 4 |SENTWORD:2|~2235~1
- 5 - C 17 AND2 s 0 3 0 1 |SENTWORD:2|~2235~2
- 5 - C 20 OR2 1 3 0 1 |SENTWORD:2|:2245
- 4 - C 15 AND2 1 1 0 1 |SENTWORD:2|:2258
- 4 - C 14 OR2 s ! 0 2 0 5 |SENTWORD:2|~2259~1
- 4 - C 20 AND2 0 4 0 1 |SENTWORD:2|:2259
- 1 - C 24 OR2 1 3 0 1 |SENTWORD:2|:2266
- 1 - C 15 OR2 1 2 0 1 |SENTWORD:2|:2293
- 2 - C 15 OR2 s 0 4 0 1 |SENTWORD:2|~2325~1
- 5 - C 15 OR2 s 0 4 0 1 |SENTWORD:2|~2325~2
- 6 - C 15 OR2 s 1 3 0 1 |SENTWORD:2|~2325~3
- 7 - C 15 OR2 s 0 4 0 1 |SENTWORD:2|~2325~4
- 8 - C 15 OR2 s 1 3 0 1 |SENTWORD:2|~2325~5
- 7 - C 20 OR2 1 3 0 1 |SENTWORD:2|:2335
- 2 - C 20 OR2 1 3 0 1 |SENTWORD:2|:2341
- 2 - C 24 OR2 1 3 0 1 |SENTWORD:2|:2347
- 3 - C 24 OR2 1 3 0 1 |SENTWORD:2|:2353
- 5 - C 24 OR2 1 3 0 1 |SENTWORD:2|:2359
- 8 - C 24 OR2 1 2 0 1 |SENTWORD:2|:2362
- 1 - C 22 OR2 s 1 3 0 1 |SENTWORD:2|~2413~1
- 2 - C 22 OR2 s 1 3 0 1 |SENTWORD:2|~2413~2
- 3 - C 22 OR2 s 1 3 0 1 |SENTWORD:2|~2413~3
- 6 - C 22 OR2 s 1 3 0 1 |SENTWORD:2|~2413~4
- 8 - C 22 OR2 s 1 3 0 1 |SENTWORD:2|~2413~5
- 5 - C 13 OR2 s 0 4 0 1 |SENTWORD:2|~2413~6
- 8 - A 17 AND2 0 2 0 4 |SERIALOUT:3|LPM_ADD_SUB:238|addcore:adder|:55
- 4 - A 17 OR2 0 3 0 2 |SERIALOUT:3|LPM_ADD_SUB:238|addcore:adder|:69
- 1 - A 16 DFFE 0 4 1 0 |SERIALOUT:3|:11
- 4 - A 16 DFFE 0 5 0 6 |SERIALOUT:3|state2 (|SERIALOUT:3|:14)
- 5 - A 16 DFFE 0 4 0 5 |SERIALOUT:3|state1 (|SERIALOUT:3|:15)
- 3 - A 24 DFFE 1 4 0 6 |SERIALOUT:3|state0 (|SERIALOUT:3|:16)
- 6 - A 24 DFFE 1 2 0 1 |SERIALOUT:3|qinbuf7 (|SERIALOUT:3|:17)
- 8 - C 13 DFFE 1 3 0 1 |SERIALOUT:3|qinbuf6 (|SERIALOUT:3|:18)
- 2 - C 17 DFFE 1 3 0 1 |SERIALOUT:3|qinbuf5 (|SERIALOUT:3|:19)
- 7 - C 21 DFFE 1 3 0 1 |SERIALOUT:3|qinbuf4 (|SERIALOUT:3|:20)
- 7 - C 17 DFFE 1 3 0 1 |SERIALOUT:3|qinbuf3 (|SERIALOUT:3|:21)
- 6 - C 17 DFFE 1 3 0 1 |SERIALOUT:3|qinbuf2 (|SERIALOUT:3|:22)
- 6 - C 21 DFFE 1 3 0 1 |SERIALOUT:3|qinbuf1 (|SERIALOUT:3|:23)
- 2 - C 21 DFFE 1 3 0 1 |SERIALOUT:3|qinbuf0 (|SERIALOUT:3|:24)
- 8 - A 23 DFFE 0 4 1 2 |SERIALOUT:3|txds (|SERIALOUT:3|:25)
- 7 - A 17 DFFE 0 3 0 4 |SERIALOUT:3|xcnt3 (|SERIALOUT:3|:26)
- 4 - A 15 DFFE 0 4 0 5 |SERIALOUT:3|xcnt2 (|SERIALOUT:3|:27)
- 5 - A 15 DFFE 0 4 0 3 |SERIALOUT:3|xcnt1 (|SERIALOUT:3|:28)
- 2 - A 15 DFFE 0 4 0 3 |SERIALOUT:3|xcnt0 (|SERIALOUT:3|:29)
- 3 - A 23 DFFE 0 4 0 1 |SERIALOUT:3|xbitcnt2 (|SERIALOUT:3|:30)
- 1 - A 23 DFFE 0 3 0 4 |SERIALOUT:3|xbitcnt1 (|SERIALOUT:3|:31)
- 2 - A 23 DFFE 0 2 0 6 |SERIALOUT:3|xbitcnt0 (|SERIALOUT:3|:32)
- 2 - A 17 OR2 ! 0 3 0 5 |SERIALOUT:3|:220
- 1 - A 17 OR2 ! 0 4 0 4 |SERIALOUT:3|:309
- 5 - A 23 OR2 0 4 0 1 |SERIALOUT:3|:494
- 1 - C 21 OR2 0 3 0 1 |SERIALOUT:3|:497
- 8 - C 21 OR2 0 3 0 1 |SERIALOUT:3|:500
- 4 - C 17 OR2 0 3 0 1 |SERIALOUT:3|:503
- 5 - C 21 OR2 0 4 0 1 |SERIALOUT:3|:507
- 4 - A 23 OR2 0 4 0 1 |SERIALOUT:3|:508
- 8 - A 16 AND2 0 3 0 7 |SERIALOUT:3|:621
- 6 - A 16 OR2 ! 0 3 0 8 |SERIALOUT:3|:631
- 2 - A 16 OR2 ! 0 3 0 8 |SERIALOUT:3|:641
- 3 - A 16 AND2 s 0 2 0 1 |SERIALOUT:3|~651~1
- 7 - A 16 AND2 0 3 0 17 |SERIALOUT:3|:651
- 2 - A 24 AND2 0 2 0 4 |SERIALOUT:3|:682
- 5 - A 24 AND2 0 2 0 1 |SERIALOUT:3|:683
- 6 - A 23 OR2 0 4 0 1 |SERIALOUT:3|:825
- 7 - A 23 OR2 0 4 0 1 |SERIALOUT:3|:833
- 3 - A 17 OR2 0 4 0 1 |SERIALOUT:3|:840
- 5 - A 17 OR2 0 4 0 1 |SERIALOUT:3|:843
- 6 - A 17 OR2 0 4 0 1 |SERIALOUT:3|:846
- 3 - A 15 OR2 s 0 4 0 3 |SERIALOUT:3|~864~1
- 1 - A 24 OR2 s 0 4 0 1 |SERIALOUT:3|~864~2
- 4 - A 24 OR2 s 0 3 0 2 |SERIALOUT:3|~864~3
- 8 - A 15 OR2 s 0 3 0 1 |SERIALOUT:3|~864~4
- 7 - A 15 OR2 s 0 3 0 1 |SERIALOUT:3|~879~1
- 1 - A 15 OR2 s 0 4 0 1 |SERIALOUT:3|~894~1
- 6 - A 15 AND2 s ! 0 4 0 3 |SERIALOUT:3|~939~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\fpga 232\232.rpt
232
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 19/ 96( 19%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 12/ 96( 12%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 38/ 96( 39%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\fpga 232\232.rpt
232
** CLOCK SIGNALS **
Type Fan-out Name
DFF 32 |FEN1250:1|:2
INPUT 12 clk
Device-Specific Information: f:\fpga 232\232.rpt
232
** EQUATIONS **
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