serialout.rpt

基于VHDL的串口通信 基于VHDL的串口通信

-- Equation name is '_LC6_B18', type is buried 
_LC6_B18 = LCELL( _EQ021);
  _EQ021 = !xcnt2 &  xcnt3
         # !_LC6_B14 &  xcnt3
         #  _LC6_B14 &  xcnt2 & !xcnt3;

-- Node name is ':11' 
-- Equation name is '_LC1_B13', type is buried 
_LC1_B13 = DFFE( _EQ022, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ022 = !state0 & !state1 & !state2;

-- Node name is ':220' 
-- Equation name is '_LC5_B14', type is buried 
!_LC5_B14 = _LC5_B14~NOT;
_LC5_B14~NOT = LCELL( _EQ023);
  _EQ023 =  xcnt3
         #  xcnt2
         # !_LC6_B14;

-- Node name is ':309' 
-- Equation name is '_LC8_B14', type is buried 
!_LC8_B14 = _LC8_B14~NOT;
_LC8_B14~NOT = LCELL( _EQ024);
  _EQ024 =  xcnt3
         #  xcnt2
         # !xcnt1
         #  xcnt0;

-- Node name is ':494' 
-- Equation name is '_LC5_B23', type is buried 
_LC5_B23 = LCELL( _EQ025);
  _EQ025 =  _LC6_B19 &  xbitcnt2
         #  _LC4_B23 &  xbitcnt2
         #  _LC2_B19 & !xbitcnt2;

-- Node name is ':497' 
-- Equation name is '_LC2_B19', type is buried 
_LC2_B19 = LCELL( _EQ026);
  _EQ026 =  _LC8_B19 &  xbitcnt1
         #  _LC4_B21 & !xbitcnt1;

-- Node name is ':500' 
-- Equation name is '_LC4_B21', type is buried 
_LC4_B21 = LCELL( _EQ027);
  _EQ027 =  qinbuf0 & !xbitcnt0
         #  qinbuf1 &  xbitcnt0;

-- Node name is ':503' 
-- Equation name is '_LC8_B19', type is buried 
_LC8_B19 = LCELL( _EQ028);
  _EQ028 =  qinbuf2 & !xbitcnt0
         #  qinbuf3 &  xbitcnt0;

-- Node name is ':507' 
-- Equation name is '_LC4_B23', type is buried 
_LC4_B23 = LCELL( _EQ029);
  _EQ029 =  qinbuf4 & !xbitcnt0 & !xbitcnt1
         #  qinbuf5 &  xbitcnt0 & !xbitcnt1;

-- Node name is ':508' 
-- Equation name is '_LC6_B19', type is buried 
_LC6_B19 = LCELL( _EQ030);
  _EQ030 =  qinbuf6 & !xbitcnt0 &  xbitcnt1
         #  qinbuf7 &  xbitcnt0 &  xbitcnt1;

-- Node name is ':621' 
-- Equation name is '_LC4_B13', type is buried 
_LC4_B13 = LCELL( _EQ031);
  _EQ031 =  state0 &  state1 & !state2;

-- Node name is ':631' 
-- Equation name is '_LC2_B13', type is buried 
!_LC2_B13 = _LC2_B13~NOT;
_LC2_B13~NOT = LCELL( _EQ032);
  _EQ032 = !state1
         #  state2
         #  state0;

-- Node name is ':641' 
-- Equation name is '_LC8_B13', type is buried 
!_LC8_B13 = _LC8_B13~NOT;
_LC8_B13~NOT = LCELL( _EQ033);
  _EQ033 =  state1
         #  state2
         # !state0;

-- Node name is ':651' 
-- Equation name is '_LC3_B13', type is buried 
_LC3_B13 = LCELL( _EQ034);
  _EQ034 = !state0 & !state1 & !state2;

-- Node name is '~656~1' 
-- Equation name is '~656~1', location is LC5_B13, type is buried.
-- synthesized logic cell 
_LC5_B13 = LCELL( _EQ035);
  _EQ035 = !_LC3_B13 & !_LC8_B13;

-- Node name is ':682' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = LCELL( _EQ036);
  _EQ036 = !_LC5_B14 &  _LC8_B13;

-- Node name is ':683' 
-- Equation name is '_LC8_B22', type is buried 
_LC8_B22 = LCELL( _EQ037);
  _EQ037 =  _LC2_B13 &  _LC8_B14;

-- Node name is ':825' 
-- Equation name is '_LC6_B23', type is buried 
_LC6_B23 = LCELL( _EQ038);
  _EQ038 =  _LC4_B13 &  _LC5_B23
         # !_LC4_B13 &  txds
         # !_LC4_B13 & !_LC5_B14;

-- Node name is ':833' 
-- Equation name is '_LC8_B23', type is buried 
_LC8_B23 = LCELL( _EQ039);
  _EQ039 = !_LC2_B13 &  _LC6_B23 & !_LC8_B13
         #  _LC2_B13 & !_LC8_B13 &  txds;

-- Node name is ':840' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = LCELL( _EQ040);
  _EQ040 = !xcnt2 &  xcnt3
         # !_LC6_B14 &  xcnt3
         # !_LC4_B13 &  _LC6_B14 &  xcnt2 & !xcnt3
         #  _LC4_B13 &  xcnt3;

-- Node name is ':843' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ041);
  _EQ041 = !_LC2_B13 &  _LC5_B18
         #  _LC2_B13 &  _LC6_B18 & !_LC8_B14;

-- Node name is ':846' 
-- Equation name is '_LC8_B18', type is buried 
_LC8_B18 = LCELL( _EQ042);
  _EQ042 =  _LC7_B18 & !_LC8_B13
         #  _LC4_B18 &  _LC6_B18;

-- Node name is '~864~1' 
-- Equation name is '~864~1', location is LC1_B21, type is buried.
-- synthesized logic cell 
_LC1_B21 = LCELL( _EQ043);
  _EQ043 = !_LC2_B13 &  _LC4_B13 & !_LC8_B13
         #  _LC3_B13;

-- Node name is '~864~2' 
-- Equation name is '~864~2', location is LC3_B18, type is buried.
-- synthesized logic cell 
_LC3_B18 = LCELL( _EQ044);
  _EQ044 =  _LC2_B13 & !_LC8_B14
         # !_LC2_B13 & !_LC4_B13 & !_LC5_B14;

-- Node name is '~864~3' 
-- Equation name is '~864~3', location is LC2_B18, type is buried.
-- synthesized logic cell 
_LC2_B18 = LCELL( _EQ045);
  _EQ045 =  _LC4_B18
         #  _LC3_B18 & !_LC8_B13;

-- Node name is '~864~4' 
-- Equation name is '~864~4', location is LC7_B14, type is buried.
-- synthesized logic cell 
_LC7_B14 = LCELL( _EQ046);
  _EQ046 = !_LC6_B14 &  xcnt2
         # !_LC3_B13 &  _LC6_B14 & !xcnt2;

-- Node name is '~879~1' 
-- Equation name is '~879~1', location is LC2_B14, type is buried.
-- synthesized logic cell 
_LC2_B14 = LCELL( _EQ047);
  _EQ047 = !xcnt0 &  xcnt1
         # !_LC3_B13 &  xcnt0 & !xcnt1;

-- Node name is '~894~1' 
-- Equation name is '~894~1', location is LC1_B23, type is buried.
-- synthesized logic cell 
_LC1_B23 = LCELL( _EQ048);
  _EQ048 =  _LC2_B13 & !_LC8_B14
         # !_LC2_B13 & !_LC4_B13
         #  _LC8_B13;

-- Node name is '~939~1' 
-- Equation name is '~939~1', location is LC8_B21, type is buried.
-- synthesized logic cell 
!_LC8_B21 = _LC8_B21~NOT;
_LC8_B21~NOT = LCELL( _EQ049);
  _EQ049 = !_LC2_B13 & !_LC3_B13 &  _LC4_B13 & !_LC8_B13;



Project Information                                  f:\fpga 232\serialout.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,275K