📄 serialout.rpt
字号:
& = Uses single-pin Output Enable
Device-Specific Information: f:\fpga 232\serialout.rpt
serialout
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 14 AND2 0 2 0 4 |LPM_ADD_SUB:238|addcore:adder|:55
- 6 - B 18 OR2 0 3 0 2 |LPM_ADD_SUB:238|addcore:adder|:69
- 1 - B 13 DFFE + 0 3 1 0 :11
- 6 - B 13 DFFE + 0 4 0 6 state2 (:14)
- 7 - B 13 DFFE + 0 3 0 5 state1 (:15)
- 1 - B 19 DFFE + 1 3 0 6 state0 (:16)
- 7 - B 19 DFFE + 2 1 0 1 qinbuf7 (:17)
- 5 - B 19 DFFE + 2 1 0 1 qinbuf6 (:18)
- 3 - B 23 DFFE + 2 1 0 1 qinbuf5 (:19)
- 2 - B 23 DFFE + 2 1 0 1 qinbuf4 (:20)
- 4 - B 19 DFFE + 2 1 0 1 qinbuf3 (:21)
- 3 - B 19 DFFE + 2 1 0 1 qinbuf2 (:22)
- 6 - B 21 DFFE + 2 1 0 1 qinbuf1 (:23)
- 3 - B 21 DFFE + 2 1 0 1 qinbuf0 (:24)
- 7 - B 23 DFFE + 0 3 1 2 txds (:25)
- 1 - B 18 DFFE + 0 2 0 4 xcnt3 (:26)
- 4 - B 14 DFFE + 0 3 0 5 xcnt2 (:27)
- 3 - B 14 DFFE + 0 3 0 3 xcnt1 (:28)
- 1 - B 14 DFFE + 0 3 0 3 xcnt0 (:29)
- 7 - B 21 DFFE + 0 3 0 1 xbitcnt2 (:30)
- 5 - B 21 DFFE + 0 2 0 4 xbitcnt1 (:31)
- 2 - B 21 DFFE + 0 1 0 6 xbitcnt0 (:32)
- 5 - B 14 OR2 ! 0 3 0 5 :220
- 8 - B 14 OR2 ! 0 4 0 4 :309
- 5 - B 23 OR2 0 4 0 1 :494
- 2 - B 19 OR2 0 3 0 1 :497
- 4 - B 21 OR2 0 3 0 1 :500
- 8 - B 19 OR2 0 3 0 1 :503
- 4 - B 23 OR2 0 4 0 1 :507
- 6 - B 19 OR2 0 4 0 1 :508
- 4 - B 13 AND2 0 3 0 7 :621
- 2 - B 13 OR2 ! 0 3 0 8 :631
- 8 - B 13 OR2 ! 0 3 0 8 :641
- 3 - B 13 AND2 0 3 0 17 :651
- 5 - B 13 AND2 s 0 2 0 1 ~656~1
- 4 - B 18 AND2 0 2 0 4 :682
- 8 - B 22 AND2 0 2 0 1 :683
- 6 - B 23 OR2 0 4 0 1 :825
- 8 - B 23 OR2 0 4 0 1 :833
- 5 - B 18 OR2 0 4 0 1 :840
- 7 - B 18 OR2 0 4 0 1 :843
- 8 - B 18 OR2 0 4 0 1 :846
- 1 - B 21 OR2 s 0 4 0 3 ~864~1
- 3 - B 18 OR2 s 0 4 0 1 ~864~2
- 2 - B 18 OR2 s 0 3 0 2 ~864~3
- 7 - B 14 OR2 s 0 3 0 1 ~864~4
- 2 - B 14 OR2 s 0 3 0 1 ~879~1
- 1 - B 23 OR2 s 0 4 0 1 ~894~1
- 8 - B 21 AND2 s ! 0 4 0 3 ~939~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\fpga 232\serialout.rpt
serialout
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 25/ 96( 26%) 0/ 48( 0%) 2/ 48( 4%) 4/16( 25%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\fpga 232\serialout.rpt
serialout
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 clk
Device-Specific Information: f:\fpga 232\serialout.rpt
serialout
** EQUATIONS **
clk : INPUT;
qin0 : INPUT;
qin1 : INPUT;
qin2 : INPUT;
qin3 : INPUT;
qin4 : INPUT;
qin5 : INPUT;
qin6 : INPUT;
qin7 : INPUT;
wr : INPUT;
-- Node name is ':24' = 'qinbuf0'
-- Equation name is 'qinbuf0', location is LC3_B21, type is buried.
qinbuf0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = qinbuf0 & !wr
# !_LC3_B13 & qinbuf0
# _LC3_B13 & qin0 & wr;
-- Node name is ':23' = 'qinbuf1'
-- Equation name is 'qinbuf1', location is LC6_B21, type is buried.
qinbuf1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = qinbuf1 & !wr
# !_LC3_B13 & qinbuf1
# _LC3_B13 & qin1 & wr;
-- Node name is ':22' = 'qinbuf2'
-- Equation name is 'qinbuf2', location is LC3_B19, type is buried.
qinbuf2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = qinbuf2 & !wr
# !_LC3_B13 & qinbuf2
# _LC3_B13 & qin2 & wr;
-- Node name is ':21' = 'qinbuf3'
-- Equation name is 'qinbuf3', location is LC4_B19, type is buried.
qinbuf3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = qinbuf3 & !wr
# !_LC3_B13 & qinbuf3
# _LC3_B13 & qin3 & wr;
-- Node name is ':20' = 'qinbuf4'
-- Equation name is 'qinbuf4', location is LC2_B23, type is buried.
qinbuf4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = qinbuf4 & !wr
# !_LC3_B13 & qinbuf4
# _LC3_B13 & qin4 & wr;
-- Node name is ':19' = 'qinbuf5'
-- Equation name is 'qinbuf5', location is LC3_B23, type is buried.
qinbuf5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = qinbuf5 & !wr
# !_LC3_B13 & qinbuf5
# _LC3_B13 & qin5 & wr;
-- Node name is ':18' = 'qinbuf6'
-- Equation name is 'qinbuf6', location is LC5_B19, type is buried.
qinbuf6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = qinbuf6 & !wr
# !_LC3_B13 & qinbuf6
# _LC3_B13 & qin6 & wr;
-- Node name is ':17' = 'qinbuf7'
-- Equation name is 'qinbuf7', location is LC7_B19, type is buried.
qinbuf7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = qinbuf7 & !wr
# !_LC3_B13 & qinbuf7
# _LC3_B13 & qin7 & wr;
-- Node name is ':16' = 'state0'
-- Equation name is 'state0', location is LC1_B19, type is buried.
state0 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC3_B13 & wr
# !_LC3_B13 & _LC8_B22
# !_LC3_B13 & _LC4_B18;
-- Node name is ':15' = 'state1'
-- Equation name is 'state1', location is LC7_B13, type is buried.
state1 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = state1 & !state2
# _LC5_B14 & state0 & !state2;
-- Node name is ':14' = 'state2'
-- Equation name is 'state2', location is LC6_B13, type is buried.
state2 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !_LC2_B13 & !_LC4_B13 & _LC5_B13 & !_LC5_B14;
-- Node name is 'tdempty'
-- Equation name is 'tdempty', type is output
tdempty = _LC1_B13;
-- Node name is 'txd'
-- Equation name is 'txd', type is output
txd = txds;
-- Node name is ':25' = 'txds'
-- Equation name is 'txds', location is LC7_B23, type is buried.
txds = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC8_B23
# _LC4_B18 & txds
# _LC3_B13;
-- Node name is ':32' = 'xbitcnt0'
-- Equation name is 'xbitcnt0', location is LC2_B21, type is buried.
xbitcnt0 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = _LC8_B21 & xbitcnt0
# !_LC8_B21 & !xbitcnt0;
-- Node name is ':31' = 'xbitcnt1'
-- Equation name is 'xbitcnt1', location is LC5_B21, type is buried.
xbitcnt1 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !xbitcnt0 & xbitcnt1
# _LC8_B21 & xbitcnt1
# !_LC8_B21 & xbitcnt0 & !xbitcnt1;
-- Node name is ':30' = 'xbitcnt2'
-- Equation name is 'xbitcnt2', location is LC7_B21, type is buried.
xbitcnt2 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !xbitcnt1 & xbitcnt2
# !xbitcnt0 & xbitcnt2
# _LC8_B21 & xbitcnt2
# !_LC8_B21 & xbitcnt0 & xbitcnt1 & !xbitcnt2;
-- Node name is ':29' = 'xcnt0'
-- Equation name is 'xcnt0', location is LC1_B14, type is buried.
xcnt0 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = _LC1_B23 & !_LC3_B13 & !xcnt0
# _LC1_B21 & xcnt0;
-- Node name is ':28' = 'xcnt1'
-- Equation name is 'xcnt1', location is LC3_B14, type is buried.
xcnt1 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = _LC2_B14 & _LC2_B18
# _LC1_B21 & xcnt1;
-- Node name is ':27' = 'xcnt2'
-- Equation name is 'xcnt2', location is LC4_B14, type is buried.
xcnt2 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = _LC2_B18 & _LC7_B14
# _LC1_B21 & xcnt2;
-- Node name is ':26' = 'xcnt3'
-- Equation name is 'xcnt3', location is LC1_B18, type is buried.
xcnt3 = DFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = !_LC3_B13 & _LC8_B18
# _LC3_B13 & xcnt3;
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = LCELL( _EQ020);
_EQ020 = xcnt0 & xcnt1;
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
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