📄 fen1250.rpt
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-- Node name is ':8' = 'cnt6'
-- Equation name is 'cnt6', location is LC8_B12, type is buried.
cnt6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = cnt6 & !_LC5_B12 & !_LC7_B12
# !cnt6 & _LC5_B12 & !_LC7_B12;
-- Node name is ':7' = 'cnt7'
-- Equation name is 'cnt7', location is LC5_B4, type is buried.
cnt7 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !cnt6 & cnt7 & !_LC7_B12
# cnt7 & !_LC5_B12 & !_LC7_B12
# cnt6 & !cnt7 & _LC5_B12 & !_LC7_B12;
-- Node name is ':6' = 'cnt8'
-- Equation name is 'cnt8', location is LC2_B8, type is buried.
cnt8 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = cnt8 & !_LC3_B12 & !_LC7_B12
# !cnt8 & _LC3_B12 & !_LC7_B12;
-- Node name is ':5' = 'cnt9'
-- Equation name is 'cnt9', location is LC2_B4, type is buried.
cnt9 = DFFE( _LC6_B4, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':4' = 'cnt10'
-- Equation name is 'cnt10', location is LC1_B4, type is buried.
cnt10 = DFFE( _LC7_B4, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'qout'
-- Equation name is 'qout', type is output
qout = _LC4_B4;
-- Node name is '|LPM_ADD_SUB:64|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B1', type is buried
_LC6_B1 = LCELL( _EQ009);
_EQ009 = cnt0 & cnt1;
-- Node name is '|LPM_ADD_SUB:64|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = LCELL( _EQ010);
_EQ010 = cnt0 & cnt1 & cnt2 & cnt3;
-- Node name is '|LPM_ADD_SUB:64|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = LCELL( _EQ011);
_EQ011 = cnt4 & cnt5 & _LC8_B1;
-- Node name is '|LPM_ADD_SUB:64|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B12', type is buried
_LC3_B12 = LCELL( _EQ012);
_EQ012 = cnt6 & cnt7 & _LC5_B12;
-- Node name is '|LPM_ADD_SUB:64|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = LCELL( _EQ013);
_EQ013 = cnt6 & cnt7 & cnt8 & _LC5_B12;
-- Node name is '|LPM_COMPARE:156|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|comptree:sub_comptree|cmpchain:gt_cmp_end|~40~1' from file "cmpchain.tdf" line 868, column 21
-- Equation name is '_LC8_B4', type is buried
-- synthesized logic cell
_LC8_B4 = LCELL( _EQ014);
_EQ014 = cnt6 & !cnt7 & _LC5_B12
# !cnt6 & cnt7
# cnt7 & !_LC5_B12
# cnt6 & !cnt8 & _LC5_B12
# !cnt6 & cnt8
# cnt8 & !_LC5_B12
# !cnt7 & cnt8;
-- Node name is '|LPM_COMPARE:156|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|comptree:sub_comptree|cmpchain:gt_cmp_end|~40~2' from file "cmpchain.tdf" line 868, column 21
-- Equation name is '_LC6_B12', type is buried
-- synthesized logic cell
_LC6_B12 = LCELL( _EQ015);
_EQ015 = cnt4 & cnt5 & cnt6 & !_LC8_B1;
-- Node name is ':2'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = _LC6_B4 & _LC8_B4
# _LC6_B4 & _LC6_B12
# _LC7_B4;
-- Node name is '~29~1'
-- Equation name is '~29~1', location is LC1_B12, type is buried.
-- synthesized logic cell
_LC1_B12 = LCELL( _EQ017);
_EQ017 = !cnt6
# cnt4
# !cnt5;
-- Node name is '~29~2'
-- Equation name is '~29~2', location is LC1_B1, type is buried.
-- synthesized logic cell
_LC1_B1 = LCELL( _EQ018);
_EQ018 = cnt8
# !cnt7
# cnt3;
-- Node name is '~29~3'
-- Equation name is '~29~3', location is LC2_B1, type is buried.
-- synthesized logic cell
_LC2_B1 = LCELL( _EQ019);
_EQ019 = cnt1
# _LC1_B1
# cnt9
# !cnt0;
-- Node name is ':29'
-- Equation name is '_LC7_B12', type is buried
!_LC7_B12 = _LC7_B12~NOT;
_LC7_B12~NOT = LCELL( _EQ020);
_EQ020 = !cnt10
# cnt2
# _LC1_B12
# _LC2_B1;
-- Node name is ':87'
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = LCELL( _EQ021);
_EQ021 = !cnt9 & cnt10 & !_LC7_B12
# cnt10 & !_LC3_B4 & !_LC7_B12
# cnt9 & !cnt10 & _LC3_B4 & !_LC7_B12;
-- Node name is ':93'
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ022);
_EQ022 = cnt9 & !_LC3_B4 & !_LC7_B12
# !cnt9 & _LC3_B4 & !_LC7_B12;
Project Information f:\fpga 232\fen1250.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,189K
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