📄 fen1250.rpt
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Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 25
Total flipflops required: 12
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 5/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 8 0 0 8 0 0 0 1 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 25/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 0 0 8 0 0 0 1 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 25/0
Device-Specific Information: f:\fpga 232\fen1250.rpt
fen1250
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
39 - - - -- INPUT G ^ 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\fpga 232\fen1250.rpt
fen1250
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
63 - - B -- OUTPUT 0 1 0 0 qout
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\fpga 232\fen1250.rpt
fen1250
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 01 AND2 0 2 0 1 |LPM_ADD_SUB:64|addcore:adder|:87
- 8 - B 01 AND2 0 4 0 4 |LPM_ADD_SUB:64|addcore:adder|:95
- 5 - B 12 AND2 0 3 0 5 |LPM_ADD_SUB:64|addcore:adder|:103
- 3 - B 12 AND2 0 3 0 1 |LPM_ADD_SUB:64|addcore:adder|:111
- 3 - B 04 AND2 0 4 0 2 |LPM_ADD_SUB:64|addcore:adder|:115
- 8 - B 04 OR2 s 0 4 0 1 |LPM_COMPARE:156|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|comptree:sub_comptree|cmpchain:gt_cmp_end|~40~1
- 6 - B 12 AND2 s 0 4 0 1 |LPM_COMPARE:156|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|comptree:sub_comptree|cmpchain:gt_cmp_end|~40~2
- 4 - B 04 DFFE + 0 4 1 0 :2
- 1 - B 04 DFFE + 0 1 0 2 cnt10 (:4)
- 2 - B 04 DFFE + 0 1 0 3 cnt9 (:5)
- 2 - B 08 DFFE + 0 2 0 3 cnt8 (:6)
- 5 - B 04 DFFE + 0 3 0 4 cnt7 (:7)
- 8 - B 12 DFFE + 0 2 0 6 cnt6 (:8)
- 2 - B 12 DFFE + 0 3 0 3 cnt5 (:9)
- 4 - B 12 DFFE + 0 2 0 4 cnt4 (:10)
- 7 - B 01 DFFE + 0 3 0 2 cnt3 (:11)
- 4 - B 01 DFFE + 0 3 0 3 cnt2 (:12)
- 5 - B 01 DFFE + 0 2 0 4 cnt1 (:13)
- 3 - B 01 DFFE + 0 0 0 5 cnt0 (:14)
- 1 - B 12 OR2 s 0 3 0 1 ~29~1
- 1 - B 01 OR2 s 0 3 0 1 ~29~2
- 2 - B 01 OR2 s 0 4 0 1 ~29~3
- 7 - B 12 OR2 ! 0 4 0 10 :29
- 7 - B 04 OR2 0 4 0 2 :87
- 6 - B 04 OR2 0 3 0 2 :93
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\fpga 232\fen1250.rpt
fen1250
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 13/ 96( 13%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\fpga 232\fen1250.rpt
fen1250
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clk
Device-Specific Information: f:\fpga 232\fen1250.rpt
fen1250
** EQUATIONS **
clk : INPUT;
-- Node name is ':14' = 'cnt0'
-- Equation name is 'cnt0', location is LC3_B1, type is buried.
cnt0 = DFFE(!cnt0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':13' = 'cnt1'
-- Equation name is 'cnt1', location is LC5_B1, type is buried.
cnt1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !cnt0 & cnt1 & !_LC7_B12
# cnt0 & !cnt1 & !_LC7_B12;
-- Node name is ':12' = 'cnt2'
-- Equation name is 'cnt2', location is LC4_B1, type is buried.
cnt2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !cnt1 & cnt2 & !_LC7_B12
# !cnt0 & cnt2 & !_LC7_B12
# cnt0 & cnt1 & !cnt2 & !_LC7_B12;
-- Node name is ':11' = 'cnt3'
-- Equation name is 'cnt3', location is LC7_B1, type is buried.
cnt3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !cnt2 & cnt3 & !_LC7_B12
# cnt3 & !_LC6_B1 & !_LC7_B12
# cnt2 & !cnt3 & _LC6_B1 & !_LC7_B12;
-- Node name is ':10' = 'cnt4'
-- Equation name is 'cnt4', location is LC4_B12, type is buried.
cnt4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = cnt4 & !_LC7_B12 & !_LC8_B1
# !cnt4 & !_LC7_B12 & _LC8_B1;
-- Node name is ':9' = 'cnt5'
-- Equation name is 'cnt5', location is LC2_B12, type is buried.
cnt5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !cnt4 & cnt5 & !_LC7_B12
# cnt5 & !_LC7_B12 & !_LC8_B1
# cnt4 & !cnt5 & !_LC7_B12 & _LC8_B1;
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