sentword.rpt

基于VHDL的串口通信 基于VHDL的串口通信

-- Equation name is '~1947~1', location is LC5_C4, type is buried.
-- synthesized logic cell 
_LC5_C4  = LCELL( _EQ028);
  _EQ028 = !state0 & !state3
         # !state0 &  state2
         # !state0 &  state1
         # !state1 & !state3
         # !state1 &  state2
         #  state0 & !state1
         #  state2 &  state3
         #  state0 &  state3
         #  state1 &  state3
         # !state2 & !state3
         #  state0 & !state2
         #  state1 & !state2;

-- Node name is ':2034' 
-- Equation name is '_LC7_C10', type is buried 
_LC7_C10 = LCELL( _EQ029);
  _EQ029 =  state1 & !state2 &  state3;

-- Node name is '~2100~1' 
-- Equation name is '~2100~1', location is LC1_C8, type is buried.
-- synthesized logic cell 
_LC1_C8  = LCELL( _EQ030);
  _EQ030 =  state3
         # !state0 &  state1
         # !state0 & !state2
         #  state0 &  state2
         #  state1 &  state2
         #  state0 & !state1
         # !state1 & !state2;

-- Node name is ':2209' 
-- Equation name is '_LC2_C10', type is buried 
_LC2_C10 = LCELL( _EQ031);
  _EQ031 = !state2 &  state3
         # !state1 &  state3;

-- Node name is '~2235~1' 
-- Equation name is '~2235~1', location is LC8_C9, type is buried.
-- synthesized logic cell 
!_LC8_C9 = _LC8_C9~NOT;
_LC8_C9~NOT = LCELL( _EQ032);
  _EQ032 = !state1 &  state2 & !state3;

-- Node name is '~2235~2' 
-- Equation name is '~2235~2', location is LC8_C6, type is buried.
-- synthesized logic cell 
_LC8_C6  = LCELL( _EQ033);
  _EQ033 = !_LC1_C11 & !_LC7_C4 &  _LC8_C9 &  _LC8_C11;

-- Node name is ':2245' 
-- Equation name is '_LC1_C6', type is buried 
_LC1_C6  = LCELL( _EQ034);
  _EQ034 = !_LC5_C2 &  _LC5_C6
         #  _LC3_C6 & !_LC5_C2
         #  _LC5_C2 &  tdempty;

-- Node name is ':2258' 
-- Equation name is '_LC4_C4', type is buried 
_LC4_C4  = LCELL( _EQ035);
  _EQ035 =  _LC3_C4 & !tdempty;

-- Node name is ':2259' 
-- Equation name is '_LC2_C6', type is buried 
_LC2_C6  = LCELL( _EQ036);
  _EQ036 =  _LC1_C6 & !_LC2_C4 & !_LC2_C8 &  _LC5_C4;

-- Node name is ':2266' 
-- Equation name is '_LC4_C6', type is buried 
_LC4_C6  = LCELL( _EQ037);
  _EQ037 =  _LC2_C6
         # !_LC8_C9
         #  _LC7_C4
         #  _LC4_C4;

-- Node name is ':2293' 
-- Equation name is '_LC1_C2', type is buried 
_LC1_C2  = LCELL( _EQ038);
  _EQ038 =  _LC2_C8
         #  _LC5_C2 & !tdempty;

-- Node name is '~2325~1' 
-- Equation name is '~2325~1', location is LC3_C2, type is buried.
-- synthesized logic cell 
_LC3_C2  = LCELL( _EQ039);
  _EQ039 =  _LC1_C2 & !_LC2_C4 &  _LC5_C4
         #  _LC7_C4;

-- Node name is '~2325~2' 
-- Equation name is '~2325~2', location is LC4_C2, type is buried.
-- synthesized logic cell 
_LC4_C2  = LCELL( _EQ040);
  _EQ040 =  _LC1_C8 &  _LC3_C2 & !_LC5_C8
         #  _LC1_C8 &  _LC4_C4 & !_LC5_C8;

-- Node name is '~2325~3' 
-- Equation name is '~2325~3', location is LC6_C2, type is buried.
-- synthesized logic cell 
_LC6_C2  = LCELL( _EQ041);
  _EQ041 =  _LC4_C2
         #  _LC1_C11 & !tdempty
         #  _LC3_C11;

-- Node name is '~2325~4' 
-- Equation name is '~2325~4', location is LC7_C2, type is buried.
-- synthesized logic cell 
_LC7_C2  = LCELL( _EQ042);
  _EQ042 =  _LC1_C8 &  _LC5_C8
         #  _LC1_C8 &  _LC2_C4 &  _LC5_C4;

-- Node name is '~2325~5' 
-- Equation name is '~2325~5', location is LC8_C2, type is buried.
-- synthesized logic cell 
_LC8_C2  = LCELL( _EQ043);
  _EQ043 =  _LC6_C2 & !_LC7_C11
         #  _LC7_C11 &  tdempty
         #  _LC7_C2 &  tdempty;

-- Node name is '~2368~1' 
-- Equation name is '~2368~1', location is LC1_C16, type is buried.
-- synthesized logic cell 
_LC1_C16 = LCELL( _EQ044);
  _EQ044 =  _LC5_C2 & !tdempty
         # !_LC5_C6 & !tdempty
         # !_LC3_C6 & !_LC5_C2 & !_LC5_C6;

-- Node name is '~2368~2' 
-- Equation name is '~2368~2', location is LC2_C16, type is buried.
-- synthesized logic cell 
_LC2_C16 = LCELL( _EQ045);
  _EQ045 =  _LC1_C16 & !_LC2_C4 & !_LC2_C8
         #  _LC2_C4 & !tdempty;

-- Node name is '~2368~3' 
-- Equation name is '~2368~3', location is LC3_C16, type is buried.
-- synthesized logic cell 
_LC3_C16 = LCELL( _EQ046);
  _EQ046 =  _LC2_C16 &  _LC5_C4
         #  _LC4_C4;

-- Node name is '~2368~4' 
-- Equation name is '~2368~4', location is LC4_C16, type is buried.
-- synthesized logic cell 
_LC4_C16 = LCELL( _EQ047);
  _EQ047 =  _LC3_C16 & !_LC5_C8 & !_LC7_C4
         #  _LC5_C8 & !tdempty;

-- Node name is '~2368~5' 
-- Equation name is '~2368~5', location is LC5_C16, type is buried.
-- synthesized logic cell 
_LC5_C16 = LCELL( _EQ048);
  _EQ048 =  _LC1_C11 & !tdempty
         #  _LC1_C8 &  _LC4_C16;

-- Node name is '~2368~6' 
-- Equation name is '~2368~6', location is LC7_C16, type is buried.
-- synthesized logic cell 
_LC7_C16 = LCELL( _EQ049);
  _EQ049 = !_LC3_C11 &  _LC5_C16 & !_LC7_C11
         #  _LC7_C11 & !tdempty;

-- Node name is '~2368~7' 
-- Equation name is '~2368~7', location is LC8_C16, type is buried.
-- synthesized logic cell 
_LC8_C16 = LCELL( _EQ050);
  _EQ050 = !state0 &  state2 & !state3
         # !state0 &  state1 & !state3
         # !state0 & !state2 &  state3
         # !state0 &  state1 & !state2
         # !state0 & !state1 &  state2;

-- Node name is '~2413~1' 
-- Equation name is '~2413~1', location is LC3_C8, type is buried.
-- synthesized logic cell 
!_LC3_C8 = _LC3_C8~NOT;
_LC3_C8~NOT = LCELL( _EQ051);
  _EQ051 =  _LC7_C4
         #  _LC5_C8;

-- Node name is '~2413~2' 
-- Equation name is '~2413~2', location is LC5_C10, type is buried.
-- synthesized logic cell 
_LC5_C10 = LCELL( _EQ052);
  _EQ052 =  _LC2_C4 & !tdempty
         # !_LC2_C8 &  _LC5_C2 & !tdempty;

-- Node name is '~2413~3' 
-- Equation name is '~2413~3', location is LC6_C8, type is buried.
-- synthesized logic cell 
_LC6_C8  = LCELL( _EQ053);
  _EQ053 =  _LC3_C4 & !tdempty
         #  _LC5_C4 &  _LC5_C10;

-- Node name is '~2413~4' 
-- Equation name is '~2413~4', location is LC8_C8, type is buried.
-- synthesized logic cell 
_LC8_C8  = LCELL( _EQ054);
  _EQ054 =  _LC5_C8 & !tdempty
         # !_LC5_C8 &  _LC6_C8 & !_LC7_C4;

-- Node name is '~2413~5' 
-- Equation name is '~2413~5', location is LC7_C8, type is buried.
-- synthesized logic cell 
_LC7_C8  = LCELL( _EQ055);
  _EQ055 =  _LC1_C11 & !tdempty
         #  _LC1_C8 &  _LC8_C8;

-- Node name is '~2413~6' 
-- Equation name is '~2413~6', location is LC4_C11, type is buried.
-- synthesized logic cell 
_LC4_C11 = LCELL( _EQ056);
  _EQ056 =  _LC7_C11 & !tdempty
         # !_LC3_C11 &  _LC7_C8 & !_LC7_C11;

-- Node name is '~2413~7' 
-- Equation name is '~2413~7', location is LC5_C11, type is buried.
-- synthesized logic cell 
_LC5_C11 = LCELL( _EQ057);
  _EQ057 = !state0 &  state2 & !state3
         # !state0 &  state1 & !state3
         # !state0 & !state2 &  state3
         # !state0 &  state1 & !state2
         # !state0 & !state1 &  state2
         # !state1 &  state2 &  state3;



Project Information                                   f:\fpga 232\sentword.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 27,881K