📄 sentword.rpt
字号:
- 2 - C 06 AND2 0 4 0 1 :2259
- 4 - C 06 OR2 0 4 0 1 :2266
- 1 - C 02 OR2 1 2 0 1 :2293
- 3 - C 02 OR2 s 0 4 0 1 ~2325~1
- 4 - C 02 OR2 s 0 4 0 1 ~2325~2
- 6 - C 02 OR2 s 1 3 0 1 ~2325~3
- 7 - C 02 OR2 s 0 4 0 1 ~2325~4
- 8 - C 02 OR2 s 1 3 0 1 ~2325~5
- 1 - C 16 OR2 s 1 3 0 1 ~2368~1
- 2 - C 16 OR2 s 1 3 0 1 ~2368~2
- 3 - C 16 OR2 s 0 3 0 1 ~2368~3
- 4 - C 16 OR2 s 1 3 0 1 ~2368~4
- 5 - C 16 OR2 s 1 3 0 1 ~2368~5
- 7 - C 16 OR2 s 1 3 0 1 ~2368~6
- 8 - C 16 OR2 s 0 4 0 1 ~2368~7
- 3 - C 08 OR2 s ! 0 2 0 1 ~2413~1
- 5 - C 10 OR2 s 1 3 0 1 ~2413~2
- 6 - C 08 OR2 s 1 3 0 1 ~2413~3
- 8 - C 08 OR2 s 1 3 0 1 ~2413~4
- 7 - C 08 OR2 s 1 3 0 1 ~2413~5
- 4 - C 11 OR2 s 1 3 0 1 ~2413~6
- 5 - C 11 OR2 s 0 4 0 1 ~2413~7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\fpga 232\sentword.rpt
sentword
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 35/144( 24%) 7/ 72( 9%) 0/ 72( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\fpga 232\sentword.rpt
sentword
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clk
Device-Specific Information: f:\fpga 232\sentword.rpt
sentword
** EQUATIONS **
clk : INPUT;
tdempty : INPUT;
-- Node name is 'qout0'
-- Equation name is 'qout0', type is output
qout0 = _LC8_C4;
-- Node name is 'qout1'
-- Equation name is 'qout1', type is output
qout1 = _LC4_C8;
-- Node name is 'qout2'
-- Equation name is 'qout2', type is output
qout2 = _LC3_C10;
-- Node name is 'qout3'
-- Equation name is 'qout3', type is output
qout3 = _LC1_C4;
-- Node name is 'qout4'
-- Equation name is 'qout4', type is output
qout4 = _LC4_C10;
-- Node name is 'qout5'
-- Equation name is 'qout5', type is output
qout5 = _LC1_C10;
-- Node name is 'qout6'
-- Equation name is 'qout6', type is output
qout6 = _LC6_C4;
-- Node name is 'qout7'
-- Equation name is 'qout7', type is output
qout7 = GND;
-- Node name is ':25' = 'state0'
-- Equation name is 'state0', location is LC6_C16, type is buried.
state0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC2_C11 & _LC7_C16
# _LC8_C16 & tdempty
# _LC2_C11 & tdempty;
-- Node name is ':24' = 'state1'
-- Equation name is 'state1', location is LC2_C2, type is buried.
state1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC2_C11 & _LC8_C2;
-- Node name is ':23' = 'state2'
-- Equation name is 'state2', location is LC6_C6, type is buried.
state2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC1_C11 & _LC4_C6 & _LC8_C11
# _LC1_C11 & _LC8_C11 & tdempty;
-- Node name is ':22' = 'state3'
-- Equation name is 'state3', location is LC7_C6, type is buried.
state3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC2_C10 & !_LC3_C4 & _LC8_C6
# _LC3_C4 & _LC8_C6 & tdempty;
-- Node name is 'wr'
-- Equation name is 'wr', type is output
wr = _LC6_C11;
-- Node name is ':3'
-- Equation name is '_LC6_C11', type is buried
_LC6_C11 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC2_C11 & _LC4_C11
# _LC5_C11 & !tdempty
# _LC2_C11 & !tdempty;
-- Node name is ':7'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = state0 & !state2 & state3
# !state0 & state1 & !state2
# !state0 & state1 & !state3
# state2 & !state3;
-- Node name is ':9'
-- Equation name is '_LC1_C10', type is buried
_LC1_C10 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC2_C10 & _LC8_C11
# _LC1_C11 & _LC8_C11
# _LC6_C10 & _LC8_C11;
-- Node name is ':11'
-- Equation name is '_LC4_C10', type is buried
_LC4_C10 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC1_C11 & _LC8_C9 & _LC8_C10 & _LC8_C11;
-- Node name is ':13'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !state1 & state2 & !state3
# state0 & !state1 & !state2 & state3
# !state0 & state1 & !state2;
-- Node name is ':15'
-- Equation name is '_LC3_C10', type is buried
_LC3_C10 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !_LC1_C11 & _LC6_C10 & _LC8_C11
# !_LC1_C11 & _LC7_C10 & _LC8_C11;
-- Node name is ':17'
-- Equation name is '_LC4_C8', type is buried
_LC4_C8 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC1_C8 & !_LC3_C8 & _LC8_C11
# _LC1_C8 & _LC2_C8 & _LC8_C11;
-- Node name is ':19'
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = state0 & state2 & !state3
# !state0 & !state1 & state2 & state3
# state0 & !state2 & state3
# !state0 & state1 & !state2;
-- Node name is ':1643'
-- Equation name is '_LC3_C6', type is buried
!_LC3_C6 = _LC3_C6~NOT;
_LC3_C6~NOT = LCELL( _EQ013);
_EQ013 = !state0
# state1
# !state3
# !state2;
-- Node name is ':1657'
-- Equation name is '_LC5_C6', type is buried
!_LC5_C6 = _LC5_C6~NOT;
_LC5_C6~NOT = LCELL( _EQ014);
_EQ014 = state0
# state1
# !state3
# !state2;
-- Node name is ':1671'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = LCELL( _EQ015);
_EQ015 = state0 & state1 & !state2 & state3;
-- Node name is ':1685'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ016);
_EQ016 = !state0 & state1 & !state2 & state3;
-- Node name is ':1699'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = LCELL( _EQ017);
_EQ017 = state0 & !state1 & !state2 & state3;
-- Node name is ':1727'
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = LCELL( _EQ018);
_EQ018 = state0 & state1 & state2 & !state3;
-- Node name is ':1741'
-- Equation name is '_LC7_C4', type is buried
_LC7_C4 = LCELL( _EQ019);
_EQ019 = !state0 & state1 & state2 & !state3;
-- Node name is ':1755'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ020);
_EQ020 = state0 & !state1 & state2 & !state3;
-- Node name is ':1783'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = LCELL( _EQ021);
_EQ021 = state0 & state1 & !state2 & !state3;
-- Node name is ':1797'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = LCELL( _EQ022);
_EQ022 = !state0 & state1 & !state2 & !state3;
-- Node name is ':1811'
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = LCELL( _EQ023);
_EQ023 = state0 & !state1 & !state2 & !state3;
-- Node name is ':1825'
-- Equation name is '_LC2_C11', type is buried
!_LC2_C11 = _LC2_C11~NOT;
_LC2_C11~NOT = LCELL( _EQ024);
_EQ024 = state3
# state2
# state0
# state1;
-- Node name is '~1861~1'
-- Equation name is '~1861~1', location is LC6_C10, type is buried.
-- synthesized logic cell
_LC6_C10 = LCELL( _EQ025);
_EQ025 = !_LC8_C9
# _LC7_C4
# _LC3_C4;
-- Node name is '~1920~1'
-- Equation name is '~1920~1', location is LC8_C11, type is buried.
-- synthesized logic cell
_LC8_C11 = LCELL( _EQ026);
_EQ026 = !_LC2_C11 & !_LC3_C11 & !_LC7_C11;
-- Node name is ':1945'
-- Equation name is '_LC8_C10', type is buried
_LC8_C10 = LCELL( _EQ027);
_EQ027 = _LC5_C2 & _LC5_C4
# _LC2_C4 & _LC5_C4
# _LC7_C4;
-- Node name is '~1947~1'
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