fcon.vhd

用FPGA实现DDS的信号发生器（正弦波125kHz）

library ieee;
use ieee.std_logic_1164.all;
entity fcon is
  port(clk :in std_logic;
       fout:out std_logic);
end entity fcon;
architecture behave of fcon is
type fcon_st is (st0,st1,st2,st3);
signal current_state :fcon_st:=st0;
signal flog :std_logic;
signal fnot :std_logic;
signal fnor :std_logic;
begin 
REG:process(clk)
    variable clkcount :integer range 0 to 50;
    variable clkcount2 :integer range 0 to 2;
    begin
      if(clk'event and clk='1') then
        clkcount:=clkcount+1;
        fnot<='1';
        if clkcount2=0 then
          case current_state is
          when st0=>flog<='1';
            if clkcount=29 then 
              clkcount:=0;
              current_state<=st1;
            end if;
          when st1=>flog<='0';
            if clkcount=10 then 
              clkcount:=0;
              current_state<=st2;
            end if;  
          when st2=>flog<='1';
            if clkcount=10 then 
              clkcount:=0;
              current_state<=st3;
            end if;  
          when st3=>flog<='0';
            if clkcount=20 then 
              clkcount:=0;
              current_state<=st0;
              clkcount2:=clkcount2+1;
            end if; 
          when others =>current_state<=st0;
            clkcount:=0;
          end case;
        else
          case current_state is
          when st0=>flog<='1';
            if clkcount=30 then 
              clkcount:=0;
              current_state<=st1;
            end if;
          when st1=>flog<='0';
            if clkcount=10 then 
              clkcount:=0;
              current_state<=st2;
            end if;  
          when st2=>flog<='1';
            if clkcount=10 then 
              clkcount:=0;
              current_state<=st3;
            end if;  
          when st3=>flog<='0';
            if clkcount=20 then 
              clkcount:=0;
              current_state<=st0;
            end if; 
          when others =>current_state<=st0;
            clkcount:=0;
          end case;
        end if; 
      end if;
   end process;
fnor<=not fnot;
fout<=flog or fnor;
end architecture;