📄 ddsmain.rpt
字号:
_LC8_A7~NOT = LCELL( _EQ052);
_EQ052 = !_LC1_F28 & _LC4_F28;
-- Node name is '|f_div:i_fdiv|:10' = '|f_div:i_fdiv|clkcounter10'
-- Equation name is '_LC2_E27', type is buried
_LC2_E27 = DFFE(!_LC2_E27, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|f_div:i_fdiv|:9' = '|f_div:i_fdiv|clkcounter11'
-- Equation name is '_LC5_E29', type is buried
_LC5_E29 = DFFE( _EQ053, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ053 = !_LC2_E27 & !_LC2_E29 & _LC5_E29
# _LC2_E27 & !_LC2_E29 & !_LC5_E29;
-- Node name is '|f_div:i_fdiv|:8' = '|f_div:i_fdiv|clkcounter12'
-- Equation name is '_LC4_E29', type is buried
_LC4_E29 = DFFE( _EQ054, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ054 = !_LC2_E29 & _LC4_E29 & !_LC5_E29
# !_LC2_E27 & !_LC2_E29 & _LC4_E29
# _LC2_E27 & !_LC2_E29 & !_LC4_E29 & _LC5_E29;
-- Node name is '|f_div:i_fdiv|:7' = '|f_div:i_fdiv|clkcounter13'
-- Equation name is '_LC1_E29', type is buried
_LC1_E29 = DFFE( _EQ055, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ055 = _LC1_E29 & !_LC5_E29
# _LC1_E29 & !_LC2_E27
# _LC1_E29 & !_LC4_E29
# !_LC1_E29 & _LC2_E27 & _LC4_E29 & _LC5_E29;
-- Node name is '|f_div:i_fdiv|:6' = '|f_div:i_fdiv|clkcounter14'
-- Equation name is '_LC6_E29', type is buried
_LC6_E29 = DFFE( _EQ056, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ056 = !_LC2_E29 & !_LC3_E29 & _LC6_E29
# !_LC2_E29 & _LC3_E29 & !_LC6_E29;
-- Node name is '|f_div:i_fdiv|:5' = '|f_div:i_fdiv|clkcounter15'
-- Equation name is '_LC7_E29', type is buried
_LC7_E29 = DFFE( _EQ057, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ057 = !_LC2_E29 & !_LC6_E29 & _LC7_E29
# !_LC2_E29 & !_LC3_E29 & _LC7_E29
# !_LC2_E29 & _LC3_E29 & _LC6_E29 & !_LC7_E29;
-- Node name is '|f_div:i_fdiv|:4' = '|f_div:i_fdiv|clkcounter16'
-- Equation name is '_LC8_E29', type is buried
_LC8_E29 = DFFE( _EQ058, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ058 = !_LC7_E29 & _LC8_E29
# !_LC6_E29 & _LC8_E29
# !_LC3_E29 & _LC8_E29
# _LC3_E29 & _LC6_E29 & _LC7_E29 & !_LC8_E29;
-- Node name is '|f_div:i_fdiv|:3' = '|f_div:i_fdiv|div_clk1'
-- Equation name is '_LC2_E24', type is buried
_LC2_E24 = DFFE( _EQ059, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ059 = _LC2_E24 & !_LC2_E29
# !_LC2_E24 & _LC2_E29;
-- Node name is '|f_div:i_fdiv|LPM_ADD_SUB:36|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_E29', type is buried
!_LC3_E29 = _LC3_E29~NOT;
_LC3_E29~NOT = LCELL( _EQ060);
_EQ060 = !_LC1_E29
# !_LC4_E29
# !_LC5_E29
# !_LC2_E27;
-- Node name is '|f_div:i_fdiv|:44'
-- Equation name is '_LC2_E29', type is buried
!_LC2_E29 = _LC2_E29~NOT;
_LC2_E29~NOT = LCELL( _EQ061);
_EQ061 = _LC6_E29
# !_LC7_E29
# _LC8_E29
# !_LC3_E29;
-- Node name is ':2'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = DFFE( _EQ062, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ062 = _EC9_C
# !_LC1_F28 & _LC4_F28;
-- Node name is ':4'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = DFFE( _EQ063, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ063 = _EC1_C & !_LC4_F28
# _EC1_C & _LC1_F28;
-- Node name is ':6'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = DFFE( _EQ064, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ064 = _EC10_C & !_LC4_F28
# _EC10_C & _LC1_F28;
-- Node name is ':8'
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = DFFE( _EQ065, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ065 = _EC10_A & !_LC4_F28
# _EC10_A & _LC1_F28;
-- Node name is ':10'
-- Equation name is '_LC2_A7', type is buried
_LC2_A7 = DFFE( _EQ066, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ066 = _EC2_A & !_LC4_F28
# _EC2_A & _LC1_F28;
-- Node name is ':12'
-- Equation name is '_LC4_A10', type is buried
_LC4_A10 = DFFE( _EQ067, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ067 = _EC9_A & !_LC4_F28
# _EC9_A & _LC1_F28;
-- Node name is ':14'
-- Equation name is '_LC2_F28', type is buried
_LC2_F28 = DFFE( _EQ068, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ068 = _EC1_A & !_LC4_F28
# _EC1_A & _LC1_F28;
-- Node name is ':16'
-- Equation name is '_LC1_C32', type is buried
_LC1_C32 = DFFE( _EQ069, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ069 = _EC2_C & !_LC4_F28
# _EC2_C & _LC1_F28;
-- Node name is '|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_C', type is memory
_EC2_C = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, VCC, VCC, VCC);
-- Node name is '|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_A', type is memory
_EC1_A = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, VCC, VCC, VCC);
-- Node name is '|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_A', type is memory
_EC9_A = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, VCC, VCC, VCC);
-- Node name is '|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_A', type is memory
_EC2_A = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, VCC, VCC, VCC);
-- Node name is '|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_A', type is memory
_EC10_A = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, VCC, VCC, VCC);
-- Node name is '|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_C', type is memory
_EC10_C = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, VCC, VCC, VCC);
-- Node name is '|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_C', type is memory
_EC1_C = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, VCC, VCC, VCC);
-- Node name is '|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_C', type is memory
_EC9_C = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, _LC6_C2, _LC3_C1, _LC3_C8, _LC7_C8, _LC5_C2, _LC7_C2, _LC4_C2, _LC1_C16, _LC3_C16, _LC6_C16, VCC, VCC, VCC, VCC);
Project Information f:\muxfile\sin125\ddsmain.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:03
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:08
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,393K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -