📄 ddsmain.rpt
字号:
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: f:\muxfile\sin125\ddsmain.rpt
ddsmain
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A7 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
A10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
C1 3/ 8( 37%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
C2 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 1/2 0/2 5/22( 22%)
C4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
C6 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
C8 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
C16 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
C32 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
E24 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
E27 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
E29 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
F21 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 7/22( 31%)
F23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
F24 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
F28 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 3/22( 13%)
F36 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A37 4/16( 25%) 1/16( 6%) 3/16( 18%) 1/2 2/6 10/88( 11%)
C37 4/16( 25%) 0/16( 0%) 4/16( 25%) 1/2 2/6 10/88( 11%)
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 10/96 ( 10%)
Total logic cells used: 74/1728 ( 4%)
Total embedded cells used: 8/96 ( 8%)
Total EABs used: 2/6 ( 33%)
Average fan-in: 2.98/4 ( 74%)
Total fan-in: 221/6912 ( 3%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 10
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 74
Total flipflops required: 49
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 9/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 3 0 0 1 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4/4
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 3 8 0 1 0 2 0 8 0 0 0 0 0 0 0 8 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 31/4
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 8 0 0 0 0 0 0 0 10/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 8 0 8 8 0 0 0 3 0 0 0 0 0 0 0 1 29/0
Total: 3 8 0 1 0 2 3 8 0 1 0 0 0 0 0 8 0 0 8 1 0 8 0 8 9 0 0 1 3 8 0 0 1 0 0 0 1 74/8
Device-Specific Information: f:\muxfile\sin125\ddsmain.rpt
ddsmain
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT G ^ 0 0 0 0 sysclk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\muxfile\sin125\ddsmain.rpt
ddsmain
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
99 - - B -- OUTPUT 0 1 0 0 clkout
41 - - - 31 OUTPUT 0 1 0 0 ddsout0
42 - - - 28 OUTPUT 0 1 0 0 ddsout1
65 - - - 09 OUTPUT 0 1 0 0 ddsout2
67 - - - 08 OUTPUT 0 1 0 0 ddsout3
68 - - - 07 OUTPUT 0 1 0 0 ddsout4
69 - - - 06 OUTPUT 0 1 0 0 ddsout5
70 - - - 05 OUTPUT 0 1 0 0 ddsout6
72 - - - 03 OUTPUT 0 1 0 0 ddsout7
100 - - A -- OUTPUT 0 1 0 0 fconout
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\muxfile\sin125\ddsmain.rpt
ddsmain
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 2 C -- MEM_SGMT 0 10 0 1 |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 1 A -- MEM_SGMT 0 10 0 1 |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 9 A -- MEM_SGMT 0 10 0 1 |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 2 A -- MEM_SGMT 0 10 0 1 |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 10 A -- MEM_SGMT 0 10 0 1 |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 10 C -- MEM_SGMT 0 10 0 1 |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 1 C -- MEM_SGMT 0 10 0 1 |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 9 C -- MEM_SGMT 0 10 0 1 |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- 4 - C 08 OR2 0 4 0 3 |ddsc2:i_ddsc|ddsc1:c1|LPM_ADD_SUB:204|addcore:adder|pcarry2
- 5 - C 08 OR2 0 4 0 3 |ddsc2:i_ddsc|ddsc1:c1|LPM_ADD_SUB:204|addcore:adder|pcarry4
- 4 - C 16 AND2 0 3 0 3 |ddsc2:i_ddsc|ddsc1:c1|LPM_ADD_SUB:204|addcore:adder|:99
- 8 - C 01 DFFE + 0 0 0 6 |ddsc2:i_ddsc|ddsc1:c1|freqw4 (|ddsc2:i_ddsc|ddsc1:c1|:58)
- 8 - C 16 DFFE + 0 4 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc19 (|ddsc2:i_ddsc|ddsc1:c1|:73)
- 5 - C 16 DFFE + 0 3 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc18 (|ddsc2:i_ddsc|ddsc1:c1|:74)
- 7 - C 16 DFFE + 0 2 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc17 (|ddsc2:i_ddsc|ddsc1:c1|:75)
- 3 - C 02 DFFE + 0 3 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc16 (|ddsc2:i_ddsc|ddsc1:c1|:76)
- 8 - C 02 DFFE + 0 2 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc15 (|ddsc2:i_ddsc|ddsc1:c1|:77)
- 1 - C 08 DFFE + 0 4 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc14 (|ddsc2:i_ddsc|ddsc1:c1|:78)
- 6 - C 08 DFFE + 0 2 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc13 (|ddsc2:i_ddsc|ddsc1:c1|:79)
- 8 - C 08 DFFE + 0 4 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc12 (|ddsc2:i_ddsc|ddsc1:c1|:80)
- 4 - C 01 DFFE + 0 3 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc11 (|ddsc2:i_ddsc|ddsc1:c1|:81)
- 2 - C 02 DFFE + 0 2 0 2 |ddsc2:i_ddsc|ddsc1:c1|acc10 (|ddsc2:i_ddsc|ddsc1:c1|:82)
- 6 - C 16 DFFE + 0 2 0 9 |ddsc2:i_ddsc|acc19 (|ddsc2:i_ddsc|:30)
- 3 - C 16 DFFE + 0 2 0 10 |ddsc2:i_ddsc|acc18 (|ddsc2:i_ddsc|:31)
- 1 - C 16 DFFE + 0 2 0 11 |ddsc2:i_ddsc|acc17 (|ddsc2:i_ddsc|:32)
- 4 - C 02 DFFE + 0 2 0 10 |ddsc2:i_ddsc|acc16 (|ddsc2:i_ddsc|:33)
- 7 - C 02 DFFE + 0 2 0 11 |ddsc2:i_ddsc|acc15 (|ddsc2:i_ddsc|:34)
- 5 - C 02 DFFE + 0 2 0 10 |ddsc2:i_ddsc|acc14 (|ddsc2:i_ddsc|:35)
- 7 - C 08 DFFE + 0 2 0 11 |ddsc2:i_ddsc|acc13 (|ddsc2:i_ddsc|:36)
- 3 - C 08 DFFE + 0 2 0 10 |ddsc2:i_ddsc|acc12 (|ddsc2:i_ddsc|:37)
- 3 - C 01 DFFE + 0 2 0 11 |ddsc2:i_ddsc|acc11 (|ddsc2:i_ddsc|:38)
- 6 - C 02 DFFE + 0 2 0 12 |ddsc2:i_ddsc|acc10 (|ddsc2:i_ddsc|:39)
- 2 - C 16 OR2 s 0 4 0 1 |ddsc2:i_ddsc|~174~1
- 1 - C 02 OR2 ! 0 4 0 10 |ddsc2:i_ddsc|:174
- 2 - C 08 OR2 ! 0 4 0 1 |ddsc2:i_ddsc|:199
- 2 - F 36 AND2 0 2 0 4 |fcon:i_fcon|LPM_ADD_SUB:62|addcore:adder|:67
- 1 - F 24 AND2 0 3 0 2 |fcon:i_fcon|LPM_ADD_SUB:62|addcore:adder|:75
- 4 - F 28 DFFE 0 1 0 9 |fcon:i_fcon|fnot (|fcon:i_fcon|:3)
- 6 - F 21 DFFE 0 4 0 6 |fcon:i_fcon|current_state1 (|fcon:i_fcon|:4)
- 5 - F 21 DFFE 0 4 0 7 |fcon:i_fcon|current_state0 (|fcon:i_fcon|:5)
- 1 - F 28 DFFE 0 2 0 9 |fcon:i_fcon|flog (|fcon:i_fcon|:6)
- 2 - F 24 DFFE 0 4 0 2 |fcon:i_fcon|clkcount5 (|fcon:i_fcon|:8)
- 7 - F 24 DFFE 0 4 0 5 |fcon:i_fcon|clkcount4 (|fcon:i_fcon|:9)
- 3 - F 24 DFFE 0 4 0 3 |fcon:i_fcon|clkcount3 (|fcon:i_fcon|:10)
- 4 - F 24 DFFE 0 4 0 6 |fcon:i_fcon|clkcount2 (|fcon:i_fcon|:11)
- 1 - F 23 DFFE 0 4 0 2 |fcon:i_fcon|clkcount1 (|fcon:i_fcon|:12)
- 6 - F 23 DFFE 0 4 0 5 |fcon:i_fcon|clkcount0 (|fcon:i_fcon|:13)
- 5 - F 23 DFFE 0 1 0 3 |fcon:i_fcon|clkcount21 (|fcon:i_fcon|:14)
- 7 - F 23 DFFE 0 4 0 2 |fcon:i_fcon|clkcount20 (|fcon:i_fcon|:15)
- 4 - F 23 OR2 ! 0 2 0 2 |fcon:i_fcon|:70
- 6 - F 24 OR2 s 0 3 0 3 |fcon:i_fcon|~93~1
- 2 - F 23 OR2 ! 0 4 0 3 |fcon:i_fcon|:93
- 2 - F 19 OR2 ! 0 4 0 4 |fcon:i_fcon|:169
- 8 - F 24 OR2 s 0 3 0 1 |fcon:i_fcon|~323~1
- 1 - F 21 OR2 ! 0 3 0 4 |fcon:i_fcon|:323
- 3 - F 21 AND2 0 2 0 2 |fcon:i_fcon|:432
- 5 - F 24 OR2 ! 0 4 0 2 |fcon:i_fcon|:579
- 7 - F 21 OR2 s 0 4 0 1 |fcon:i_fcon|~1022~1
- 3 - F 23 OR2 s 0 4 0 1 |fcon:i_fcon|~1022~2
- 8 - F 23 OR2 s 0 4 0 4 |fcon:i_fcon|~1040~1
- 2 - F 21 OR2 s 0 4 0 2 |fcon:i_fcon|~1040~2
- 8 - F 21 OR2 s 0 4 0 3 |fcon:i_fcon|~1052~1
- 4 - F 21 AND2 s 0 2 0 1 |fcon:i_fcon|~1071~1
- 8 - A 07 AND2 ! 0 2 1 0 |fcon:i_fcon|:1123
- 3 - E 29 OR2 ! 0 4 0 4 |f_div:i_fdiv|LPM_ADD_SUB:36|addcore:adder|:129
- 2 - E 24 DFFE + 0 1 1 12 |f_div:i_fdiv|div_clk1 (|f_div:i_fdiv|:3)
- 8 - E 29 DFFE + 0 3 0 1 |f_div:i_fdiv|clkcounter16 (|f_div:i_fdiv|:4)
- 7 - E 29 DFFE + 0 3 0 2 |f_div:i_fdiv|clkcounter15 (|f_div:i_fdiv|:5)
- 6 - E 29 DFFE + 0 2 0 3 |f_div:i_fdiv|clkcounter14 (|f_div:i_fdiv|:6)
- 1 - E 29 DFFE + 0 3 0 1 |f_div:i_fdiv|clkcounter13 (|f_div:i_fdiv|:7)
- 4 - E 29 DFFE + 0 3 0 2 |f_div:i_fdiv|clkcounter12 (|f_div:i_fdiv|:8)
- 5 - E 29 DFFE + 0 2 0 3 |f_div:i_fdiv|clkcounter11 (|f_div:i_fdiv|:9)
- 2 - E 27 DFFE + 0 0 0 4 |f_div:i_fdiv|clkcounter10 (|f_div:i_fdiv|:10)
- 2 - E 29 OR2 ! 0 4 0 5 |f_div:i_fdiv|:44
- 1 - C 04 DFFE + 0 3 1 0 :2
- 4 - C 06 DFFE + 0 3 1 0 :4
- 1 - C 06 DFFE + 0 3 1 0 :6
- 1 - A 07 DFFE + 0 3 1 0 :8
- 2 - A 07 DFFE + 0 3 1 0 :10
- 4 - A 10 DFFE + 0 3 1 0 :12
- 2 - F 28 DFFE + 0 3 1 0 :14
- 1 - C 32 DFFE + 0 3 1 0 :16
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
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