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📄 ddsmain.rpt

📁 用FPGA实现DDS的信号发生器(正弦波125kHz)
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Project Information                              f:\muxfile\sin125\ddsmain.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/25/2007 21:18:09

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


DDSMAIN


** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

ddsmain   EP1K30TC144-1    1      10     0    8192      33 %    74       4  %

User Pins:                 1      10     0  



Project Information                              f:\muxfile\sin125\ddsmain.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Memory width (8) differs from MIF width (10) -- ignoring MIF value
Warning: MIF syntax error: expected END keyword
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:53' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:54' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:55' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:56' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:57' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:59' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:61' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:72' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:63' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:64' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:65' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:66' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:67' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:68' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:69' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:70' stuck at GND
Warning: Flipflop '|ddsc2:i_ddsc|ddsc1:c1|:71' stuck at GND


Project Information                              f:\muxfile\sin125\ddsmain.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

ddsmain@99                        clkout
ddsmain@41                        ddsout0
ddsmain@42                        ddsout1
ddsmain@65                        ddsout2
ddsmain@67                        ddsout3
ddsmain@68                        ddsout4
ddsmain@69                        ddsout5
ddsmain@70                        ddsout6
ddsmain@72                        ddsout7
ddsmain@126                       sysclk


Project Information                              f:\muxfile\sin125\ddsmain.rpt

** EMBEDDED ARRAYS **


|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|content: MEMORY (
               width        =    8;
               depth        = 1024;
               segmentsize  = 1024;
               mode         = MEM_READONLY#MEM_INITIALIZED#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0;
               file         = "F:/muxfile/sin125/sin.mif";
         )
         OF SEGMENTS (
               |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_7,
               |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_6,
               |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_5,
               |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_4,
               |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_3,
               |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_2,
               |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_1,
               |ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
);




Project Information                              f:\muxfile\sin125\ddsmain.rpt

** FILE HIERARCHY **



|f_div:i_fdiv|
|f_div:i_fdiv|lpm_add_sub:36|
|f_div:i_fdiv|lpm_add_sub:36|addcore:adder|
|f_div:i_fdiv|lpm_add_sub:36|altshift:result_ext_latency_ffs|
|f_div:i_fdiv|lpm_add_sub:36|altshift:carry_ext_latency_ffs|
|f_div:i_fdiv|lpm_add_sub:36|altshift:oflow_ext_latency_ffs|
|fcon:i_fcon|
|fcon:i_fcon|lpm_add_sub:62|
|fcon:i_fcon|lpm_add_sub:62|addcore:adder|
|fcon:i_fcon|lpm_add_sub:62|altshift:result_ext_latency_ffs|
|fcon:i_fcon|lpm_add_sub:62|altshift:carry_ext_latency_ffs|
|fcon:i_fcon|lpm_add_sub:62|altshift:oflow_ext_latency_ffs|
|fcon:i_fcon|lpm_add_sub:337|
|fcon:i_fcon|lpm_add_sub:337|addcore:adder|
|fcon:i_fcon|lpm_add_sub:337|altshift:result_ext_latency_ffs|
|fcon:i_fcon|lpm_add_sub:337|altshift:carry_ext_latency_ffs|
|fcon:i_fcon|lpm_add_sub:337|altshift:oflow_ext_latency_ffs|
|ddsc2:i_ddsc|
|ddsc2:i_ddsc|ddsc1:c1|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:204|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:204|addcore:adder|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:204|altshift:result_ext_latency_ffs|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:204|altshift:carry_ext_latency_ffs|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:204|altshift:oflow_ext_latency_ffs|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:461|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:461|addcore:adder|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:461|altshift:result_ext_latency_ffs|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:461|altshift:carry_ext_latency_ffs|
|ddsc2:i_ddsc|ddsc1:c1|lpm_add_sub:461|altshift:oflow_ext_latency_ffs|
|ddsc2:i_ddsc|datarom1:u1|
|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|
|ddsc2:i_ddsc|datarom1:u1|lpm_rom:lpm_rom_component|altrom:srom|


Device-Specific Information:                     f:\muxfile\sin125\ddsmain.rpt
ddsmain

***** Logic for device 'ddsmain' compiled without errors.




Device: EP1K30TC144-1

ACEX 1K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF
    Enable Lock Output                         = OFF

                                                                                         
                                                                                         
                R R R R R   R R R R   R R R R   R           R R R R R R R   R R R R R R  
                E E E E E   E E E E   E E E E   E           E E E E E E E   E E E E E E  
                S S S S S   S S S S   S S S S   S V s       S S S S S S S   S S S S S S  
                E E E E E   E E E E V E E E E   E C y       E E E E E E E V E E E E E E  
                R R R R R   R R R R C R R R R   R C s       R R R R R R R C R R R R R R  
                V V V V V G V V V V C V V V V G V I c G G G V V V V V V V C V V V V V V  
                E E E E E N E E E E I E E E E N E N l N N N E E E E E E E I E E E E E E  
                D D D D D D D D D D O D D D D D D T k D D D D D D D D D D O D D D D D D  
              --------------------------------------------------------------------------_ 
             / 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110   |_ 
            /    143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109    | 
      #TCK |  1                                                                         108 | ^DATA0 
^CONF_DONE |  2                                                                         107 | ^DCLK 
     ^nCEO |  3                                                                         106 | ^nCE 
      #TDO |  4                                                                         105 | #TDI 
     VCCIO |  5                                                                         104 | GND 
       GND |  6                                                                         103 | VCCINT 
  RESERVED |  7                                                                         102 | RESERVED 
  RESERVED |  8                                                                         101 | RESERVED 
  RESERVED |  9                                                                         100 | fconout 
  RESERVED | 10                                                                          99 | clkout 
  RESERVED | 11                                                                          98 | RESERVED 
  RESERVED | 12                                                                          97 | RESERVED 
  RESERVED | 13                                                                          96 | RESERVED 
  RESERVED | 14                                                                          95 | RESERVED 
       GND | 15                                                                          94 | VCCIO 
    VCCINT | 16                                                                          93 | GND 
  RESERVED | 17                                                                          92 | RESERVED 
  RESERVED | 18                                                                          91 | RESERVED 
  RESERVED | 19                              EP1K30TC144-1                               90 | RESERVED 
  RESERVED | 20                                                                          89 | RESERVED 
  RESERVED | 21                                                                          88 | RESERVED 
  RESERVED | 22                                                                          87 | RESERVED 
  RESERVED | 23                                                                          86 | RESERVED 
     VCCIO | 24                                                                          85 | VCCINT 
       GND | 25                                                                          84 | GND 
  RESERVED | 26                                                                          83 | RESERVED 
  RESERVED | 27                                                                          82 | RESERVED 
  RESERVED | 28                                                                          81 | RESERVED 
  RESERVED | 29                                                                          80 | RESERVED 
  RESERVED | 30                                                                          79 | RESERVED 
  RESERVED | 31                                                                          78 | RESERVED 
  RESERVED | 32                                                                          77 | ^MSEL0 
  RESERVED | 33                                                                          76 | ^MSEL1 
      #TMS | 34                                                                          75 | VCCINT 
  ^nSTATUS | 35                                                                          74 | ^nCONFIG 
  RESERVED | 36                                                                          73 | RESERVED 
           |      38  40  42  44  46  48  50  52  54  56  58  60  62  64  66  68  70  72  _| 
            \   37  39  41  43  45  47  49  51  53  55  57  59  61  63  65  67  69  71   | 
             \--------------------------------------------------------------------------- 
                R R R G d d R R V R R R R V R G V G G G G G R R V R R R d G d d d d V d  
                E E E N d d E E C E E E E C E N C N N N N N E E C E E E d N d d d d C d  
                S S S D s s S S C S S S S C S D C D D D D D S S C S S S s D s s s s C s  
                E E E   o o E E I E E E E I E   _       _   E E I E E E o   o o o o I o  
                R R R   u u R R O R R R R N R   C       C   R R O R R R u   u u u u O u  
                V V V   t t V V   V V V V T V   K       K   V V   V V V t   t t t t   t  
                E E E   0 1 E E   E E E E   E   L       L   E E   E E E 2   3 4 5 6   7  
                D D D       D D   D D D D   D   K       K   D D   D D D                  
                                                                                         
                                                                                         


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).

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