ddsmain.vhd

用FPGA实现DDS的信号发生器（正弦波125kHz）

library ieee;
use ieee.std_logic_1164.all;
entity ddsmain is
  port(sysclk : in std_logic;
       ddsout : out std_logic_vector(7 downto 0);
       clkout,fconout : out std_logic);
       --selok : in std_logic;
      --pfsel : in std_logic;
      -- fpin : in std_logic_vector(9 downto 0));
end entity ddsmain;
architecture behave of ddsmain is
  component f_div is
    port(mclkin	:in	std_logic;
			clkout6m	:out	std_logic);
  end component f_div;
  component fcon is
    port(clk :in std_logic;
       fout:out std_logic);
  end component fcon;
  component ddsc2 is
    generic(
            freq_width : integer :=10;
            phase_width : integer :=10;
            adder_width : integer :=10;
            romad_width : integer :=10;
            rom_d_width : integer :=8);
    port(clk : in std_logic;
         freqin : in std_logic_vector(freq_width-1 downto 0);
         phasein : in std_logic_vector(phase_width-1 downto 0);
         ddsout : out std_logic_vector(rom_d_width-1 downto 0));
  end component ddsc2;
  signal clkcnt : integer range 4 downto 0;
  signal clk : std_logic;
  signal mclk: std_logic;
  signal flog: std_logic;
  signal freqind : std_logic_vector(9 downto 0);
  signal phaseind : std_logic_vector(9 downto 0);
  signal sin125 : std_logic_vector(7 downto 0);
begin
  i_fdiv :f_div                                                                                                                                                                                                                                                                                                                                                                                                            
    port map(mclkin=>clk,clkout6m=>mclk);
  i_fcon :fcon
    port map(clk=>mclk,fout=>flog);
  i_ddsc :ddsc2
    port map(clk=>clk,ddsout=>sin125,
             phasein=>phaseind,freqin=>freqind);
  clk<=sysclk;
  clkout<=mclk;
  freqind<="0000010101";
  phaseind<="0000000000";
  fconout<=flog;
  PROCESS(sysclk) 
  BEGIN
    IF(sysclk'event and sysclk='1') THEN
      if flog='1' then
         ddsout<=sin125;
      else
         ddsout<="10000000";
      end if;
    END IF;
  END PROCESS;
end architecture behave;