ddsc2.vhd

用FPGA实现DDS的信号发生器（正弦波125kHz）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library lpm;
use lpm.lpm_components.all;
entity ddsc2 is
  generic(freq_width : integer :=10;
          phase_width : integer :=10;
          adder_width : integer :=10;
          romad_width : integer :=10;
          rom_d_width : integer :=8);
  port(clk : in std_logic;
       freqin : in std_logic_vector(freq_width-1 downto 0);
       phasein : in std_logic_vector(phase_width-1 downto 0);
       ddsout : out std_logic_vector(rom_d_width-1 downto 0));
end entity ddsc2;
architecture behave of ddsc2 is
component datarom1
  port(address : in std_logic_vector(9 downto 0);
       inclock : in std_logic;
       q : out std_logic_vector(7 downto 0));
end component;
component ddsc1 is
    generic(
            freq_width : integer :=10;
            phase_width : integer :=10;
            adder_width : integer :=10;
            romad_width : integer :=10;
            rom_d_width : integer :=8);
    port(clk1 : in std_logic;
       acc : in std_logic_vector(adder_width-1 downto 0);
       freqin1 : in std_logic_vector(freq_width-1 downto 0);
       phasein1 : in std_logic_vector(phase_width-1 downto 0);
       accout: out std_logic_vector(adder_width-1 downto 0);
       ddsout : out std_logic_vector(romad_width downto 0));
end component ddsc1;
  signal acc: std_logic_vector(adder_width-1 downto 0);
  signal acc1: std_logic_vector(adder_width-1 downto 0);
  signal romaddrs: std_logic_vector(romad_width-1 downto 0);
  signal romaddr : std_logic_vector(romad_width downto 0);
  signal freqw: std_logic_vector(freq_width-1 downto 0);
  signal phasew: std_logic_vector(phase_width-1 downto 0);
begin
c1:ddsc1 
   port map(clk1=>clk,ddsout=>romaddr,accout=>acc,acc=>acc1,
             phasein1=>phasein,freqin1=>freqin);
  process(clk)
  begin
    if(clk'event and clk='1') then
      if conv_integer(romaddr)>1006 then
        acc1<="0000000000";
        romaddrs<="0000000000";
      else
        acc1<=acc;
        romaddrs<=romaddr(9 downto 0);
      end if;
    end if;
  end process;
u1:datarom1 PORT MAP(inclock=>clk,address=>romaddrs,q=>ddsout);
end architecture behave;