📄 top_clock.rpt
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_EQ016 = _LC6_B5 & !_LC7_B5 & !_LC8_B5
# !_LC4_B5 & _LC6_B5 & !_LC7_B5
# _LC4_B5 & !_LC6_B5 & !_LC7_B5 & _LC8_B5;
-- Node name is '|counter10:U1|:43'
-- Equation name is '_LC8_B5', type is buried
_LC8_B5 = DFFE( _EQ017, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ017 = !_LC4_B5 & !_LC7_B5 & _LC8_B5
# _LC4_B5 & !_LC7_B5 & !_LC8_B5;
-- Node name is '|counter10:U1|:44'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = DFFE(!_LC4_B5, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
-- Node name is '|counter10:U3|lpm_add_sub:45|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B14', type is buried
_LC4_B14 = LCELL( _EQ018);
_EQ018 = _LC1_B14 & _LC5_B14;
-- Node name is '|counter10:U3|lpm_add_sub:45|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B14', type is buried
_LC7_B14 = LCELL( _EQ019);
_EQ019 = _LC1_B14 & _LC2_B14 & _LC5_B14;
-- Node name is '|counter10:U3|:14'
-- Equation name is '_LC3_B14', type is buried
!_LC3_B14 = _LC3_B14~NOT;
_LC3_B14~NOT = LCELL( _EQ020);
_EQ020 = _LC2_B14
# _LC5_B14
# !_LC6_B14
# !_LC1_B14;
-- Node name is '|counter10:U3|:41'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = DFFE( _EQ021, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ021 = !_LC2_C15 & _LC6_B14
# !_LC3_B14 & _LC6_B14 & !_LC7_B14
# _LC2_C15 & !_LC3_B14 & !_LC6_B14 & _LC7_B14;
-- Node name is '|counter10:U3|:42'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = DFFE( _EQ022, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ022 = _LC2_B14 & !_LC3_B14 & !_LC4_B14
# !_LC2_B14 & _LC2_C15 & !_LC3_B14 & _LC4_B14
# _LC2_B14 & !_LC2_C15;
-- Node name is '|counter10:U3|:43'
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = DFFE( _EQ023, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ023 = !_LC2_C15 & _LC5_B14
# !_LC1_B14 & !_LC3_B14 & _LC5_B14
# _LC1_B14 & _LC2_C15 & !_LC3_B14 & !_LC5_B14;
-- Node name is '|counter10:U3|:44'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = DFFE( _EQ024, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ024 = !_LC1_B14 & _LC2_C15
# _LC1_B14 & !_LC2_C15;
-- Node name is '|counter24:U5|:134'
-- Equation name is '_LC4_C17', type is buried
_LC4_C17 = LCELL( _EQ025);
_EQ025 = !_LC1_C17 & _LC2_C17 & !_LC5_C17;
-- Node name is '|counter24:U5|:142'
-- Equation name is '_LC2_C17', type is buried
_LC2_C17 = LCELL( _EQ026);
_EQ026 = !_LC7_C15
# !_LC1_C15;
-- Node name is '|counter24:U5|~150~1'
-- Equation name is '_LC3_C20', type is buried
-- synthesized logic cell
_LC3_C20 = LCELL( _EQ027);
_EQ027 = _LC1_C20 & !_LC3_C15 & !_LC3_C19 & !_LC4_C17;
-- Node name is '|counter24:U5|:156'
-- Equation name is '_LC6_C17', type is buried
!_LC6_C17 = _LC6_C17~NOT;
_LC6_C17~NOT = LCELL( _EQ028);
_EQ028 = !_LC1_C17
# _LC5_C17
# _LC7_C15
# !_LC1_C15;
-- Node name is '|counter24:U5|~181~1'
-- Equation name is '_LC7_C20', type is buried
-- synthesized logic cell
_LC7_C20 = LCELL( _EQ029);
_EQ029 = !_LC6_C17
# _LC3_C20 & !_LC8_C20;
-- Node name is '|counter24:U5|~191~1'
-- Equation name is '_LC8_C17', type is buried
-- synthesized logic cell
_LC8_C17 = LCELL( _EQ030);
_EQ030 = _LC1_C17 & !_LC5_C17 & _LC7_C20
# _LC1_C17 & _LC2_C17 & _LC7_C20
# !_LC1_C17 & !_LC2_C17 & _LC5_C17 & _LC7_C20;
-- Node name is '|counter24:U5|~192~1'
-- Equation name is '_LC7_C17', type is buried
-- synthesized logic cell
_LC7_C17 = LCELL( _EQ031);
_EQ031 = _LC2_C17 & _LC5_C17 & _LC7_C20
# !_LC2_C17 & !_LC5_C17 & _LC7_C20;
-- Node name is '|counter24:U5|~193~1'
-- Equation name is '_LC8_C15', type is buried
-- synthesized logic cell
_LC8_C15 = LCELL( _EQ032);
_EQ032 = !_LC1_C15 & _LC7_C15 & _LC7_C20
# _LC1_C15 & !_LC7_C15 & _LC7_C20;
-- Node name is '|counter24:U5|:208'
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = DFFE( _EQ033, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ033 = _LC5_C20 & _LC8_C17
# _LC1_C17 & !_LC5_C15;
-- Node name is '|counter24:U5|:209'
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = DFFE( _EQ034, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ034 = _LC5_C20 & _LC7_C17
# !_LC5_C15 & _LC5_C17;
-- Node name is '|counter24:U5|:210'
-- Equation name is '_LC7_C15', type is buried
_LC7_C15 = DFFE( _EQ035, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ035 = _LC5_C20 & _LC8_C15
# !_LC5_C15 & _LC7_C15;
-- Node name is '|counter24:U5|:211'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = DFFE( _EQ036, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ036 = !_LC1_C15 & _LC5_C20
# _LC1_C15 & !_LC5_C15;
-- Node name is '|counter24:U5|:262'
-- Equation name is '_LC6_C20', type is buried
_LC6_C20 = LCELL( _EQ037);
_EQ037 = _LC1_C20 & !_LC8_C20
# !_LC1_C20 & _LC6_C17 & _LC8_C20
# _LC1_C20 & !_LC6_C17
# _LC3_C20 & !_LC8_C20;
-- Node name is '|counter24:U5|~274~1'
-- Equation name is '_LC3_C17', type is buried
-- synthesized logic cell
_LC3_C17 = LCELL( _EQ038);
_EQ038 = !_LC1_C17
# !_LC5_C17 & !_LC7_C15;
-- Node name is '|counter24:U5|~274~2'
-- Equation name is '_LC2_C20', type is buried
-- synthesized logic cell
_LC2_C20 = LCELL( _EQ039);
_EQ039 = !_LC1_C20 & _LC3_C17
# _LC3_C17 & _LC4_C17 & !_LC8_C20;
-- Node name is '|counter24:U5|~274~3'
-- Equation name is '_LC5_C20', type is buried
-- synthesized logic cell
_LC5_C20 = LCELL( _EQ040);
_EQ040 = _LC2_C20 & !_LC3_C15 & !_LC3_C19 & _LC5_C15;
-- Node name is '|counter24:U5|~275~1'
-- Equation name is '_LC4_C20', type is buried
-- synthesized logic cell
_LC4_C20 = LCELL( _EQ041);
_EQ041 = !_LC6_C17 & _LC8_C20
# !_LC3_C20 & _LC6_C17 & !_LC8_C20;
-- Node name is '|counter24:U5|:281'
-- Equation name is '_LC3_C19', type is buried
_LC3_C19 = DFFE( _EQ042, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ042 = _LC3_C19 & !_LC5_C15;
-- Node name is '|counter24:U5|:282'
-- Equation name is '_LC3_C15', type is buried
_LC3_C15 = DFFE( _EQ043, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ043 = _LC3_C15 & !_LC5_C15;
-- Node name is '|counter24:U5|:283'
-- Equation name is '_LC1_C20', type is buried
_LC1_C20 = DFFE( _EQ044, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ044 = _LC5_C20 & _LC6_C20
# _LC1_C20 & !_LC5_C15;
-- Node name is '|counter24:U5|:284'
-- Equation name is '_LC8_C20', type is buried
_LC8_C20 = DFFE( _EQ045, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ045 = _LC4_C20 & _LC5_C20
# !_LC5_C15 & _LC8_C20;
-- Node name is ':29'
-- Equation name is '_LC7_B5', type is buried
!_LC7_B5 = _LC7_B5~NOT;
_LC7_B5~NOT = LCELL( _EQ046);
_EQ046 = _LC8_B5
# !_LC1_B5
# _LC6_B5
# !_LC4_B5;
-- Node name is ':43'
-- Equation name is '_LC2_C15', type is buried
!_LC2_C15 = _LC2_C15~NOT;
_LC2_C15~NOT = LCELL( _EQ047);
_EQ047 = !Adj_Min & !_LC4_C15;
-- Node name is '~68~1'
-- Equation name is '~68~1', location is LC4_C15, type is buried.
-- synthesized logic cell
!_LC4_C15 = _LC4_C15~NOT;
_LC4_C15~NOT = LCELL( _EQ048);
_EQ048 = !_LC7_A13
# !_LC7_B5;
-- Node name is ':69'
-- Equation name is '_LC6_C15', type is buried
!_LC6_C15 = _LC6_C15~NOT;
_LC6_C15~NOT = LCELL( _EQ049);
_EQ049 = !Adj_Min & !_LC4_C15
# !_LC3_B14;
-- Node name is ':90'
-- Equation name is '_LC5_C15', type is buried
!_LC5_C15 = _LC5_C15~NOT;
_LC5_C15~NOT = LCELL( _EQ050);
_EQ050 = !Adj_Hour & !_LC2_C13
# !Adj_Hour & !_LC3_B14
# !Adj_Hour & !_LC4_C15;
Project Information f:\workhard\top_clock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,987K
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