📄 counter24.rpt
字号:
C: 3/ 96( 3%) 0/ 48( 0%) 12/ 48( 25%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\workhard\counter24.rpt
counter24
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CP
Device-Specific Information: f:\workhard\counter24.rpt
counter24
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 nCR
Device-Specific Information: f:\workhard\counter24.rpt
counter24
** EQUATIONS **
CP : INPUT;
EN : INPUT;
nCR : INPUT;
-- Node name is 'CntH0'
-- Equation name is 'CntH0', type is output
CntH0 = _LC5_C18;
-- Node name is 'CntH1'
-- Equation name is 'CntH1', type is output
CntH1 = _LC1_C21;
-- Node name is 'CntH2'
-- Equation name is 'CntH2', type is output
CntH2 = _LC7_C21;
-- Node name is 'CntH3'
-- Equation name is 'CntH3', type is output
CntH3 = _LC3_C21;
-- Node name is 'CntL0'
-- Equation name is 'CntL0', type is output
CntL0 = _LC5_C13;
-- Node name is 'CntL1'
-- Equation name is 'CntL1', type is output
CntL1 = _LC1_C13;
-- Node name is 'CntL2'
-- Equation name is 'CntL2', type is output
CntL2 = _LC2_C18;
-- Node name is 'CntL3'
-- Equation name is 'CntL3', type is output
CntL3 = _LC4_C13;
-- Node name is '|lpm_add_sub:297|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = LCELL( _EQ001);
_EQ001 = _LC1_C13 & _LC2_C18 & _LC5_C13;
-- Node name is '~104~1'
-- Equation name is '~104~1', location is LC4_C21, type is buried.
-- synthesized logic cell
_LC4_C21 = LCELL( _EQ002);
_EQ002 = !_LC3_C21 & !_LC7_C21;
-- Node name is '~104~2'
-- Equation name is '~104~2', location is LC1_C18, type is buried.
-- synthesized logic cell
_LC1_C18 = LCELL( _EQ003);
_EQ003 = !_LC2_C18 & !_LC4_C13 & !_LC5_C18 & _LC8_C13;
-- Node name is ':142'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = LCELL( _EQ004);
_EQ004 = !_LC1_C13
# !_LC5_C13;
-- Node name is ':149'
-- Equation name is '_LC5_C21', type is buried
_LC5_C21 = LCELL( _EQ005);
_EQ005 = _LC1_C18 & _LC1_C21 & !_LC3_C21 & !_LC7_C21;
-- Node name is ':155'
-- Equation name is '_LC3_C13', type is buried
!_LC3_C13 = _LC3_C13~NOT;
_LC3_C13~NOT = LCELL( _EQ006);
_EQ006 = !_LC4_C13
# _LC2_C18
# _LC1_C13
# !_LC5_C13;
-- Node name is ':180'
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ007);
_EQ007 = _LC1_C13 & !_LC3_C13 & !_LC5_C13
# _LC1_C13 & !_LC5_C13 & _LC5_C21
# !_LC1_C13 & !_LC3_C13 & _LC5_C13
# !_LC1_C13 & _LC5_C13 & _LC5_C21;
-- Node name is '~190~1'
-- Equation name is '~190~1', location is LC2_C13, type is buried.
-- synthesized logic cell
_LC2_C13 = LCELL( _EQ008);
_EQ008 = !_LC3_C13 & !_LC5_C21 & _LC6_C21;
-- Node name is ':207'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = DFFE( _EQ009, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ009 = _LC2_C13 & _LC4_C13 & !_LC7_C13
# _LC2_C13 & !_LC4_C13 & _LC7_C13
# !EN & _LC4_C13;
-- Node name is ':208'
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = DFFE( _EQ010, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ010 = _LC2_C13 & _LC2_C18 & _LC8_C13
# _LC2_C13 & !_LC2_C18 & !_LC8_C13
# !EN & _LC2_C18;
-- Node name is ':209'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = DFFE( _EQ011, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ011 = _LC6_C13 & _LC6_C21
# !EN & _LC1_C13;
-- Node name is ':210'
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = DFFE( _EQ012, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ012 = !_LC5_C13 & _LC6_C21
# !EN & _LC5_C13;
-- Node name is ':261'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = LCELL( _EQ013);
_EQ013 = _LC1_C21 & !_LC5_C18
# !_LC1_C21 & _LC3_C13 & _LC5_C18
# _LC1_C21 & !_LC3_C13
# _LC5_C21;
-- Node name is '~273~1'
-- Equation name is '~273~1', location is LC2_C21, type is buried.
-- synthesized logic cell
_LC2_C21 = LCELL( _EQ014);
_EQ014 = EN & !_LC4_C13
# EN & !_LC1_C13 & !_LC2_C18;
-- Node name is '~273~2'
-- Equation name is '~273~2', location is LC6_C21, type is buried.
-- synthesized logic cell
_LC6_C21 = LCELL( _EQ015);
_EQ015 = !_LC1_C21 & _LC2_C21 & _LC4_C21
# _LC1_C18 & _LC2_C21 & _LC4_C21;
-- Node name is '~274~1'
-- Equation name is '~274~1', location is LC3_C18, type is buried.
-- synthesized logic cell
_LC3_C18 = LCELL( _EQ016);
_EQ016 = !_LC3_C13 & _LC5_C18 & !_LC5_C21
# _LC3_C13 & !_LC5_C18 & !_LC5_C21;
-- Node name is ':280'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = DFFE( _EQ017, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ017 = !EN & _LC3_C21;
-- Node name is ':281'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = DFFE( _EQ018, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ018 = !EN & _LC7_C21;
-- Node name is ':282'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = DFFE( _EQ019, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ019 = _LC6_C21 & _LC8_C21
# !EN & _LC1_C21;
-- Node name is ':283'
-- Equation name is '_LC5_C18', type is buried
_LC5_C18 = DFFE( _EQ020, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ020 = _LC3_C18 & _LC6_C21
# !EN & _LC5_C18;
Project Information f:\workhard\counter24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,190K
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