📄 top_clock.rpt
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-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = DFFE( _EQ011, !_LC6_A21, GLOBAL( nCR), VCC, VCC);
_EQ011 = _LC1_A16 & !_LC1_A21 & _LC2_A16 & !_LC5_A16
# !_LC1_A16 & !_LC1_A21 & _LC2_A16 & _LC5_A16;
-- Node name is '|counter24:UT3|:210'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = DFFE( _EQ012, !_LC6_A21, GLOBAL( nCR), VCC, VCC);
_EQ012 = !_LC1_A21 & !_LC5_A16;
-- Node name is '|counter24:UT3|~261~1'
-- Equation name is '_LC7_A21', type is buried
-- synthesized logic cell
_LC7_A21 = LCELL( _EQ013);
_EQ013 = !_LC3_A21 & _LC8_A21
# _LC3_A21 & _LC6_A16 & !_LC8_A21
# !_LC6_A16 & _LC8_A21;
-- Node name is '|counter24:UT3|:282'
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = DFFE( _EQ014, !_LC6_A21, GLOBAL( nCR), VCC, VCC);
_EQ014 = !_LC1_A21 & _LC7_A21
# !_LC1_A21 & _LC4_A21 & _LC8_A21;
-- Node name is '|counter24:UT3|:283'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = DFFE( _EQ015, !_LC6_A21, GLOBAL( nCR), VCC, VCC);
_EQ015 = !_LC1_A21 & !_LC2_A21 & _LC3_A21 & !_LC6_A16
# !_LC1_A21 & !_LC2_A21 & !_LC3_A21 & _LC6_A16;
-- Node name is '|counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B9', type is buried
_LC3_B9 = LCELL( _EQ016);
_EQ016 = _LC4_B9 & _LC6_B3;
-- Node name is '|counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = LCELL( _EQ017);
_EQ017 = _LC4_B9 & _LC5_B9 & _LC6_B3;
-- Node name is '|counter60:UT1|counter6:UC1|:14'
-- Equation name is '_LC2_B3', type is buried
!_LC2_B3 = _LC2_B3~NOT;
_LC2_B3~NOT = LCELL( _EQ018);
_EQ018 = !_LC5_B9
# _LC6_B3
# _LC1_B12
# !_LC4_B9;
-- Node name is '|counter60:UT1|counter6:UC1|:41'
-- Equation name is '_LC1_B12', type is buried
_LC1_B12 = DFFE( _EQ019, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ019 = _LC1_B12 & !_LC2_B9
# _LC1_B12 & !_LC2_B3 & !_LC2_B12
# !_LC1_B12 & !_LC2_B3 & _LC2_B9 & _LC2_B12;
-- Node name is '|counter60:UT1|counter6:UC1|:42'
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = DFFE( _EQ020, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ020 = !_LC2_B9 & _LC5_B9
# !_LC2_B3 & !_LC3_B9 & _LC5_B9
# !_LC2_B3 & _LC2_B9 & _LC3_B9 & !_LC5_B9;
-- Node name is '|counter60:UT1|counter6:UC1|:43'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = DFFE( _EQ021, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ021 = !_LC2_B9 & _LC6_B3
# !_LC2_B3 & !_LC4_B9 & _LC6_B3
# !_LC2_B3 & _LC2_B9 & _LC4_B9 & !_LC6_B3;
-- Node name is '|counter60:UT1|counter6:UC1|:44'
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = DFFE( _EQ022, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ022 = _LC2_B9 & !_LC4_B9
# !_LC2_B9 & _LC4_B9;
-- Node name is '|counter60:UT1|counter10:UC0|:41'
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = DFFE( _EQ023, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ023 = _LC6_B9 & !_LC8_B9
# _LC1_B9 & !_LC6_B9 & _LC7_B9 & _LC8_B9
# !_LC1_B9 & _LC6_B9 & _LC7_B9
# _LC1_B9 & _LC6_B9 & !_LC7_B9;
-- Node name is '|counter60:UT1|counter10:UC0|:42'
-- Equation name is '_LC7_B9', type is buried
_LC7_B9 = DFFE( _EQ024, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ024 = !_LC1_B9 & !_LC2_B9 & _LC7_B9
# !_LC2_B9 & _LC7_B9 & !_LC8_B9
# _LC1_B9 & !_LC2_B9 & !_LC7_B9 & _LC8_B9;
-- Node name is '|counter60:UT1|counter10:UC0|:43'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = DFFE( _EQ025, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ025 = _LC1_B9 & !_LC2_B9 & !_LC8_B9
# !_LC1_B9 & !_LC2_B9 & _LC8_B9;
-- Node name is '|counter60:UT1|counter10:UC0|:44'
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = DFFE(!_LC8_B9, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
-- Node name is '|counter60:UT1|:12'
-- Equation name is '_LC2_B9', type is buried
!_LC2_B9 = _LC2_B9~NOT;
_LC2_B9~NOT = LCELL( _EQ026);
_EQ026 = _LC1_B9
# !_LC6_B9
# _LC7_B9
# !_LC8_B9;
-- Node name is '|counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ027);
_EQ027 = _LC1_B3 & _LC4_B11;
-- Node name is '|counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = LCELL( _EQ028);
_EQ028 = _LC1_B3 & _LC4_B11 & _LC5_B11;
-- Node name is '|counter60:UT2|counter6:UC1|:14'
-- Equation name is '_LC3_B3', type is buried
!_LC3_B3 = _LC3_B3~NOT;
_LC3_B3~NOT = LCELL( _EQ029);
_EQ029 = !_LC5_B11
# _LC1_B3
# _LC8_B3
# !_LC4_B11;
-- Node name is '|counter60:UT2|counter6:UC1|:41'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = DFFE( _EQ030, !_LC4_B3, GLOBAL( nCR), VCC, VCC);
_EQ030 = !_LC1_B11 & _LC8_B3
# !_LC3_B3 & !_LC7_B3 & _LC8_B3
# _LC1_B11 & !_LC3_B3 & _LC7_B3 & !_LC8_B3;
-- Node name is '|counter60:UT2|counter6:UC1|:42'
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = DFFE( _EQ031, !_LC4_B3, GLOBAL( nCR), VCC, VCC);
_EQ031 = !_LC1_B11 & _LC5_B11
# !_LC2_B11 & !_LC3_B3 & _LC5_B11
# _LC1_B11 & _LC2_B11 & !_LC3_B3 & !_LC5_B11;
-- Node name is '|counter60:UT2|counter6:UC1|:43'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = DFFE( _EQ032, !_LC4_B3, GLOBAL( nCR), VCC, VCC);
_EQ032 = _LC1_B3 & !_LC1_B11
# _LC1_B3 & !_LC3_B3 & !_LC4_B11
# !_LC1_B3 & _LC1_B11 & !_LC3_B3 & _LC4_B11;
-- Node name is '|counter60:UT2|counter6:UC1|:44'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = DFFE( _EQ033, !_LC4_B3, GLOBAL( nCR), VCC, VCC);
_EQ033 = _LC1_B11 & !_LC4_B11
# !_LC1_B11 & _LC4_B11;
-- Node name is '|counter60:UT2|counter10:UC0|:41'
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = DFFE( _EQ034, !_LC4_B3, GLOBAL( nCR), VCC, VCC);
_EQ034 = !_LC3_B11 & _LC8_B11
# _LC3_B11 & _LC6_B11 & _LC7_B11 & !_LC8_B11
# !_LC6_B11 & _LC7_B11 & _LC8_B11
# _LC6_B11 & !_LC7_B11 & _LC8_B11;
-- Node name is '|counter60:UT2|counter10:UC0|:42'
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = DFFE( _EQ035, !_LC4_B3, GLOBAL( nCR), VCC, VCC);
_EQ035 = !_LC1_B11 & !_LC6_B11 & _LC7_B11
# !_LC1_B11 & !_LC3_B11 & _LC7_B11
# !_LC1_B11 & _LC3_B11 & _LC6_B11 & !_LC7_B11;
-- Node name is '|counter60:UT2|counter10:UC0|:43'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = DFFE( _EQ036, !_LC4_B3, GLOBAL( nCR), VCC, VCC);
_EQ036 = !_LC1_B11 & !_LC3_B11 & _LC6_B11
# !_LC1_B11 & _LC3_B11 & !_LC6_B11;
-- Node name is '|counter60:UT2|counter10:UC0|:44'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = DFFE(!_LC3_B11, !_LC4_B3, GLOBAL( nCR), VCC, VCC);
-- Node name is '|counter60:UT2|:12'
-- Equation name is '_LC1_B11', type is buried
!_LC1_B11 = _LC1_B11~NOT;
_LC1_B11~NOT = LCELL( _EQ037);
_EQ037 = _LC6_B11
# !_LC8_B11
# _LC7_B11
# !_LC3_B11;
-- Node name is ':38'
-- Equation name is '_LC4_B3', type is buried
!_LC4_B3 = _LC4_B3~NOT;
_LC4_B3~NOT = LCELL( _EQ038);
_EQ038 = !Adj_Min & !_LC2_B3
# !Adj_Min & !_LC2_B9
# !CP & !_LC2_B3
# !CP & !_LC2_B9
# Adj_Min & !CP;
-- Node name is ':63'
-- Equation name is '_LC6_A21', type is buried
!_LC6_A21 = _LC6_A21~NOT;
_LC6_A21~NOT = LCELL( _EQ039);
_EQ039 = !Adj_Hour & _LC5_B3
# !CP & _LC5_B3
# Adj_Hour & !CP;
-- Node name is '~65~1'
-- Equation name is '~65~1', location is LC5_B3, type is buried.
-- synthesized logic cell
_LC5_B3 = LCELL( _EQ040);
_EQ040 = !_LC3_B3
# !_LC1_B11
# !_LC2_B3
# !_LC2_B9;
Project Information f:\workhard\top_clock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,416K
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