📄 top_clock.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\workhard\top_clock.rpt
top_clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 21 AND2 ! 0 2 0 1 |counter24:UT3|:58
- 4 - A 21 AND2 s 0 4 0 3 |counter24:UT3|~104~1
- 1 - A 21 OR2 ! 0 4 0 5 |counter24:UT3|:104
- 3 - A 16 OR2 0 2 0 3 |counter24:UT3|:142
- 2 - A 21 AND2 0 2 0 3 |counter24:UT3|:149
- 6 - A 16 OR2 ! 0 4 0 4 |counter24:UT3|:155
- 2 - A 16 OR2 s 0 2 0 1 |counter24:UT3|~180~1
- 7 - A 16 AND2 s 0 3 0 2 |counter24:UT3|~182~1
- 8 - A 16 DFFE 0 4 1 3 |counter24:UT3|:207
- 4 - A 16 DFFE 0 3 1 4 |counter24:UT3|:208
- 1 - A 16 DFFE 0 4 1 3 |counter24:UT3|:209
- 5 - A 16 DFFE 0 2 1 3 |counter24:UT3|:210
- 7 - A 21 OR2 s 0 3 0 1 |counter24:UT3|~261~1
- 8 - A 21 DFFE 0 4 1 3 |counter24:UT3|:282
- 3 - A 21 DFFE 0 4 1 2 |counter24:UT3|:283
- 3 - B 09 AND2 0 2 0 1 |counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 2 - B 12 AND2 0 3 0 1 |counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 2 - B 03 OR2 ! 0 4 0 5 |counter60:UT1|counter6:UC1|:14
- 1 - B 12 DFFE + 0 3 1 1 |counter60:UT1|counter6:UC1|:41
- 5 - B 09 DFFE + 0 3 1 2 |counter60:UT1|counter6:UC1|:42
- 6 - B 03 DFFE + 0 3 1 3 |counter60:UT1|counter6:UC1|:43
- 4 - B 09 DFFE + 0 1 1 4 |counter60:UT1|counter6:UC1|:44
- 6 - B 09 DFFE + 0 3 1 1 |counter60:UT1|counter10:UC0|:41
- 7 - B 09 DFFE + 0 3 1 2 |counter60:UT1|counter10:UC0|:42
- 1 - B 09 DFFE + 0 2 1 3 |counter60:UT1|counter10:UC0|:43
- 8 - B 09 DFFE + 0 0 1 4 |counter60:UT1|counter10:UC0|:44
- 2 - B 09 OR2 ! 0 4 0 8 |counter60:UT1|:12
- 2 - B 11 AND2 0 2 0 1 |counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 7 - B 03 AND2 0 3 0 1 |counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 3 - B 03 OR2 ! 0 4 0 4 |counter60:UT2|counter6:UC1|:14
- 8 - B 03 DFFE 0 4 1 1 |counter60:UT2|counter6:UC1|:41
- 5 - B 11 DFFE 0 4 1 2 |counter60:UT2|counter6:UC1|:42
- 1 - B 03 DFFE 0 4 1 3 |counter60:UT2|counter6:UC1|:43
- 4 - B 11 DFFE 0 2 1 4 |counter60:UT2|counter6:UC1|:44
- 8 - B 11 DFFE 0 4 1 1 |counter60:UT2|counter10:UC0|:41
- 7 - B 11 DFFE 0 4 1 2 |counter60:UT2|counter10:UC0|:42
- 6 - B 11 DFFE 0 3 1 3 |counter60:UT2|counter10:UC0|:43
- 3 - B 11 DFFE 0 1 1 4 |counter60:UT2|counter10:UC0|:44
- 1 - B 11 OR2 ! 0 4 0 7 |counter60:UT2|:12
- 4 - B 03 OR2 ! 2 2 0 8 :38
- 6 - A 21 OR2 ! 2 1 0 6 :63
- 5 - B 03 OR2 s 0 4 0 1 ~65~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\workhard\top_clock.rpt
top_clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 1/ 48( 2%) 11/ 48( 22%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 6/ 96( 6%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\workhard\top_clock.rpt
top_clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 CP
LCELL 8 :38
LCELL 6 :63
Device-Specific Information: f:\workhard\top_clock.rpt
top_clock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 22 nCR
Device-Specific Information: f:\workhard\top_clock.rpt
top_clock
** EQUATIONS **
Adj_Hour : INPUT;
Adj_Min : INPUT;
CP : INPUT;
nCR : INPUT;
-- Node name is 'Hour0'
-- Equation name is 'Hour0', type is output
Hour0 = _LC5_A16;
-- Node name is 'Hour1'
-- Equation name is 'Hour1', type is output
Hour1 = _LC1_A16;
-- Node name is 'Hour2'
-- Equation name is 'Hour2', type is output
Hour2 = _LC4_A16;
-- Node name is 'Hour3'
-- Equation name is 'Hour3', type is output
Hour3 = _LC8_A16;
-- Node name is 'Hour4'
-- Equation name is 'Hour4', type is output
Hour4 = _LC3_A21;
-- Node name is 'Hour5'
-- Equation name is 'Hour5', type is output
Hour5 = _LC8_A21;
-- Node name is 'Hour6'
-- Equation name is 'Hour6', type is output
Hour6 = GND;
-- Node name is 'Hour7'
-- Equation name is 'Hour7', type is output
Hour7 = GND;
-- Node name is 'Minute0'
-- Equation name is 'Minute0', type is output
Minute0 = _LC3_B11;
-- Node name is 'Minute1'
-- Equation name is 'Minute1', type is output
Minute1 = _LC6_B11;
-- Node name is 'Minute2'
-- Equation name is 'Minute2', type is output
Minute2 = _LC7_B11;
-- Node name is 'Minute3'
-- Equation name is 'Minute3', type is output
Minute3 = _LC8_B11;
-- Node name is 'Minute4'
-- Equation name is 'Minute4', type is output
Minute4 = _LC4_B11;
-- Node name is 'Minute5'
-- Equation name is 'Minute5', type is output
Minute5 = _LC1_B3;
-- Node name is 'Minute6'
-- Equation name is 'Minute6', type is output
Minute6 = _LC5_B11;
-- Node name is 'Minute7'
-- Equation name is 'Minute7', type is output
Minute7 = _LC8_B3;
-- Node name is 'Second0'
-- Equation name is 'Second0', type is output
Second0 = _LC8_B9;
-- Node name is 'Second1'
-- Equation name is 'Second1', type is output
Second1 = _LC1_B9;
-- Node name is 'Second2'
-- Equation name is 'Second2', type is output
Second2 = _LC7_B9;
-- Node name is 'Second3'
-- Equation name is 'Second3', type is output
Second3 = _LC6_B9;
-- Node name is 'Second4'
-- Equation name is 'Second4', type is output
Second4 = _LC4_B9;
-- Node name is 'Second5'
-- Equation name is 'Second5', type is output
Second5 = _LC6_B3;
-- Node name is 'Second6'
-- Equation name is 'Second6', type is output
Second6 = _LC5_B9;
-- Node name is 'Second7'
-- Equation name is 'Second7', type is output
Second7 = _LC1_B12;
-- Node name is '|counter24:UT3|:58'
-- Equation name is '_LC5_A21', type is buried
!_LC5_A21 = _LC5_A21~NOT;
_LC5_A21~NOT = LCELL( _EQ001);
_EQ001 = !_LC1_A16 & !_LC4_A16;
-- Node name is '|counter24:UT3|~104~1'
-- Equation name is '_LC4_A21', type is buried
-- synthesized logic cell
_LC4_A21 = LCELL( _EQ002);
_EQ002 = _LC3_A16 & !_LC3_A21 & !_LC4_A16 & !_LC8_A16;
-- Node name is '|counter24:UT3|:104'
-- Equation name is '_LC1_A21', type is buried
!_LC1_A21 = _LC1_A21~NOT;
_LC1_A21~NOT = LCELL( _EQ003);
_EQ003 = !_LC8_A16 & !_LC8_A21
# _LC4_A21 & !_LC8_A16
# !_LC5_A21 & !_LC8_A21
# _LC4_A21 & !_LC5_A21;
-- Node name is '|counter24:UT3|:142'
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = LCELL( _EQ004);
_EQ004 = !_LC1_A16
# !_LC5_A16;
-- Node name is '|counter24:UT3|:149'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ005);
_EQ005 = _LC4_A21 & _LC8_A21;
-- Node name is '|counter24:UT3|:155'
-- Equation name is '_LC6_A16', type is buried
!_LC6_A16 = _LC6_A16~NOT;
_LC6_A16~NOT = LCELL( _EQ006);
_EQ006 = !_LC8_A16
# _LC4_A16
# _LC1_A16
# !_LC5_A16;
-- Node name is '|counter24:UT3|~180~1'
-- Equation name is '_LC2_A16', type is buried
-- synthesized logic cell
_LC2_A16 = LCELL( _EQ007);
_EQ007 = !_LC6_A16
# _LC2_A21;
-- Node name is '|counter24:UT3|~182~1'
-- Equation name is '_LC7_A16', type is buried
-- synthesized logic cell
_LC7_A16 = LCELL( _EQ008);
_EQ008 = !_LC1_A21 & !_LC2_A21 & !_LC6_A16;
-- Node name is '|counter24:UT3|:207'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = DFFE( _EQ009, !_LC6_A21, GLOBAL( nCR), VCC, VCC);
_EQ009 = !_LC4_A16 & _LC7_A16 & _LC8_A16
# _LC3_A16 & _LC7_A16 & _LC8_A16
# !_LC3_A16 & _LC4_A16 & _LC7_A16 & !_LC8_A16;
-- Node name is '|counter24:UT3|:208'
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = DFFE( _EQ010, !_LC6_A21, GLOBAL( nCR), VCC, VCC);
_EQ010 = _LC3_A16 & _LC4_A16 & _LC7_A16
# !_LC3_A16 & !_LC4_A16 & _LC7_A16;
-- Node name is '|counter24:UT3|:209'
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