📄 radio.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\workhard\radio.rpt
radio
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 03 AND2 s 3 0 0 1 Minute7~1
- 2 - B 03 AND2 s 4 0 0 1 ~83~1
- 3 - B 03 AND2 s 4 0 0 1 ~83~2
- 4 - B 03 AND2 s 4 0 0 1 ~83~3
- 5 - B 03 AND2 s 1 3 0 1 ~83~4
- 6 - B 03 OR2 2 2 1 0 :83
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\workhard\radio.rpt
radio
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 9/ 96( 9%) 4/ 48( 8%) 0/ 48( 0%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\workhard\radio.rpt
radio
** EQUATIONS **
Minute0 : INPUT;
Minute1 : INPUT;
Minute2 : INPUT;
Minute3 : INPUT;
Minute4 : INPUT;
Minute5 : INPUT;
Minute6 : INPUT;
Minute7 : INPUT;
Second0 : INPUT;
Second1 : INPUT;
Second2 : INPUT;
Second3 : INPUT;
Second4 : INPUT;
Second5 : INPUT;
Second6 : INPUT;
Second7 : INPUT;
_1kHz : INPUT;
_500Hz : INPUT;
-- Node name is 'ALARM_Radio'
-- Equation name is 'ALARM_Radio', type is output
ALARM_Radio = _LC6_B3;
-- Node name is 'Minute7~1'
-- Equation name is 'Minute7~1', location is LC1_B3, type is buried.
-- synthesized logic cell
_LC1_B3 = LCELL( _EQ001);
_EQ001 = !Second1 & !Second2 & _1kHz;
-- Node name is '~83~1'
-- Equation name is '~83~1', location is LC2_B3, type is buried.
-- synthesized logic cell
_LC2_B3 = LCELL( _EQ002);
_EQ002 = !Minute2 & Minute3 & Minute4 & !Minute5;
-- Node name is '~83~2'
-- Equation name is '~83~2', location is LC3_B3, type is buried.
-- synthesized logic cell
_LC3_B3 = LCELL( _EQ003);
_EQ003 = Minute0 & !Minute1 & Second6 & !Second7;
-- Node name is '~83~3'
-- Equation name is '~83~3', location is LC4_B3, type is buried.
-- synthesized logic cell
_LC4_B3 = LCELL( _EQ004);
_EQ004 = !Minute7 & Second0 & Second4 & !Second5;
-- Node name is '~83~4'
-- Equation name is '~83~4', location is LC5_B3, type is buried.
-- synthesized logic cell
_LC5_B3 = LCELL( _EQ005);
_EQ005 = _LC2_B3 & _LC3_B3 & _LC4_B3 & Minute6;
-- Node name is ':83'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = LCELL( _EQ006);
_EQ006 = _LC1_B3 & _LC5_B3 & Second3
# _LC5_B3 & !Second3 & _500Hz;
Project Information f:\workhard\radio.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,133K
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