📄 top_clock.rpt
字号:
- 2 - B 01 DFFE 1 3 1 5 |counter24:UT3|:209
- 1 - B 01 DFFE 1 2 1 4 |counter24:UT3|:210
- 7 - B 10 OR2 0 4 0 1 |counter24:UT3|:261
- 6 - B 15 OR2 s 1 3 0 1 |counter24:UT3|~273~1
- 3 - B 10 OR2 s 0 4 0 5 |counter24:UT3|~273~2
- 6 - B 10 OR2 s 0 3 0 1 |counter24:UT3|~274~1
- 8 - B 08 DFFE 1 1 1 2 |counter24:UT3|:280
- 5 - B 08 DFFE 1 1 1 2 |counter24:UT3|:281
- 1 - B 10 DFFE 1 3 1 3 |counter24:UT3|:282
- 4 - B 10 DFFE 1 3 1 3 |counter24:UT3|:283
- 3 - C 21 AND2 0 2 0 1 |counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 8 - C 21 AND2 0 3 0 1 |counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 1 - C 21 OR2 ! 0 4 0 5 |counter60:UT1|counter6:UC1|:14
- 5 - C 21 DFFE + 0 3 1 1 |counter60:UT1|counter6:UC1|:41
- 4 - C 21 DFFE + 0 3 1 2 |counter60:UT1|counter6:UC1|:42
- 6 - C 21 DFFE + 0 3 1 3 |counter60:UT1|counter6:UC1|:43
- 7 - C 21 DFFE + 0 1 1 4 |counter60:UT1|counter6:UC1|:44
- 8 - B 15 AND2 0 3 0 1 |counter60:UT1|counter10:UC0|lpm_add_sub:45|addcore:adder|:59
- 4 - B 15 OR2 0 3 0 1 |counter60:UT1|counter10:UC0|lpm_add_sub:45|addcore:adder|:68
- 3 - B 15 DFFE + 1 2 1 1 |counter60:UT1|counter10:UC0|:41
- 5 - B 15 DFFE + 1 2 1 3 |counter60:UT1|counter10:UC0|:42
- 2 - B 15 DFFE + 1 2 1 3 |counter60:UT1|counter10:UC0|:43
- 7 - B 15 DFFE + 1 0 1 4 |counter60:UT1|counter10:UC0|:44
- 1 - B 15 OR2 ! 0 4 0 9 |counter60:UT1|:12
- 2 - C 18 AND2 0 2 0 1 |counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 4 - C 18 AND2 0 3 0 1 |counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 1 - C 18 OR2 ! 0 4 0 4 |counter60:UT2|counter6:UC1|:14
- 8 - C 18 DFFE 0 4 1 1 |counter60:UT2|counter6:UC1|:41
- 7 - C 18 DFFE 0 4 1 2 |counter60:UT2|counter6:UC1|:42
- 6 - C 18 DFFE 0 4 1 3 |counter60:UT2|counter6:UC1|:43
- 4 - C 23 DFFE 0 2 1 4 |counter60:UT2|counter6:UC1|:44
- 8 - C 23 AND2 0 3 0 1 |counter60:UT2|counter10:UC0|lpm_add_sub:45|addcore:adder|:59
- 7 - C 23 OR2 0 3 0 1 |counter60:UT2|counter10:UC0|lpm_add_sub:45|addcore:adder|:68
- 5 - C 23 DFFE 1 3 1 1 |counter60:UT2|counter10:UC0|:41
- 3 - C 23 DFFE 1 3 1 3 |counter60:UT2|counter10:UC0|:42
- 6 - C 23 DFFE 1 3 1 3 |counter60:UT2|counter10:UC0|:43
- 1 - C 23 DFFE 1 1 1 4 |counter60:UT2|counter10:UC0|:44
- 2 - C 23 OR2 ! 0 4 0 8 |counter60:UT2|:12
- 2 - C 21 OR2 ! 2 2 0 8 :39
- 3 - C 18 OR2 ! 2 1 0 8 :64
- 5 - C 18 OR2 s 0 4 0 1 ~66~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\workhard\workhard\workhard\top_clock.rpt
top_clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 8/ 96( 8%) 11/ 48( 22%) 1/ 48( 2%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 8/ 48( 16%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\workhard\workhard\workhard\top_clock.rpt
top_clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 CP
LCELL 8 :39
LCELL 8 :64
Device-Specific Information: f:\workhard\workhard\workhard\top_clock.rpt
top_clock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 24 nCR
Device-Specific Information: f:\workhard\workhard\workhard\top_clock.rpt
top_clock
** EQUATIONS **
Adj_Hour : INPUT;
Adj_Min : INPUT;
CP : INPUT;
EN : INPUT;
nCR : INPUT;
-- Node name is 'Hour0'
-- Equation name is 'Hour0', type is output
Hour0 = _LC1_B1;
-- Node name is 'Hour1'
-- Equation name is 'Hour1', type is output
Hour1 = _LC2_B1;
-- Node name is 'Hour2'
-- Equation name is 'Hour2', type is output
Hour2 = _LC3_B1;
-- Node name is 'Hour3'
-- Equation name is 'Hour3', type is output
Hour3 = _LC7_B1;
-- Node name is 'Hour4'
-- Equation name is 'Hour4', type is output
Hour4 = _LC4_B10;
-- Node name is 'Hour5'
-- Equation name is 'Hour5', type is output
Hour5 = _LC1_B10;
-- Node name is 'Hour6'
-- Equation name is 'Hour6', type is output
Hour6 = _LC5_B8;
-- Node name is 'Hour7'
-- Equation name is 'Hour7', type is output
Hour7 = _LC8_B8;
-- Node name is 'Minute0'
-- Equation name is 'Minute0', type is output
Minute0 = _LC1_C23;
-- Node name is 'Minute1'
-- Equation name is 'Minute1', type is output
Minute1 = _LC6_C23;
-- Node name is 'Minute2'
-- Equation name is 'Minute2', type is output
Minute2 = _LC3_C23;
-- Node name is 'Minute3'
-- Equation name is 'Minute3', type is output
Minute3 = _LC5_C23;
-- Node name is 'Minute4'
-- Equation name is 'Minute4', type is output
Minute4 = _LC4_C23;
-- Node name is 'Minute5'
-- Equation name is 'Minute5', type is output
Minute5 = _LC6_C18;
-- Node name is 'Minute6'
-- Equation name is 'Minute6', type is output
Minute6 = _LC7_C18;
-- Node name is 'Minute7'
-- Equation name is 'Minute7', type is output
Minute7 = _LC8_C18;
-- Node name is 'Second0'
-- Equation name is 'Second0', type is output
Second0 = _LC7_B15;
-- Node name is 'Second1'
-- Equation name is 'Second1', type is output
Second1 = _LC2_B15;
-- Node name is 'Second2'
-- Equation name is 'Second2', type is output
Second2 = _LC5_B15;
-- Node name is 'Second3'
-- Equation name is 'Second3', type is output
Second3 = _LC3_B15;
-- Node name is 'Second4'
-- Equation name is 'Second4', type is output
Second4 = _LC7_C21;
-- Node name is 'Second5'
-- Equation name is 'Second5', type is output
Second5 = _LC6_C21;
-- Node name is 'Second6'
-- Equation name is 'Second6', type is output
Second6 = _LC4_C21;
-- Node name is 'Second7'
-- Equation name is 'Second7', type is output
Second7 = _LC5_C21;
-- Node name is '|counter24:UT3|lpm_add_sub:297|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = LCELL( _EQ001);
_EQ001 = _LC1_B1 & _LC2_B1 & _LC3_B1;
-- Node name is '|counter24:UT3|~104~1'
-- Equation name is '_LC2_B10', type is buried
-- synthesized logic cell
_LC2_B10 = LCELL( _EQ002);
_EQ002 = !_LC5_B8 & !_LC8_B8;
-- Node name is '|counter24:UT3|~104~2'
-- Equation name is '_LC5_B10', type is buried
-- synthesized logic cell
_LC5_B10 = LCELL( _EQ003);
_EQ003 = !_LC3_B1 & _LC4_B7 & !_LC4_B10 & !_LC7_B1;
-- Node name is '|counter24:UT3|:142'
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = LCELL( _EQ004);
_EQ004 = !_LC2_B1
# !_LC1_B1;
-- Node name is '|counter24:UT3|:149'
-- Equation name is '_LC8_B10', type is buried
_LC8_B10 = LCELL( _EQ005);
_EQ005 = _LC1_B10 & !_LC5_B8 & _LC5_B10 & !_LC8_B8;
-- Node name is '|counter24:UT3|:155'
-- Equation name is '_LC5_B1', type is buried
!_LC5_B1 = _LC5_B1~NOT;
_LC5_B1~NOT = LCELL( _EQ006);
_EQ006 = !_LC7_B1
# _LC3_B1
# _LC2_B1
# !_LC1_B1;
-- Node name is '|counter24:UT3|:180'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = LCELL( _EQ007);
_EQ007 = !_LC1_B1 & _LC2_B1 & !_LC5_B1
# !_LC1_B1 & _LC2_B1 & _LC8_B10
# _LC1_B1 & !_LC2_B1 & !_LC5_B1
# _LC1_B1 & !_LC2_B1 & _LC8_B10;
-- Node name is '|counter24:UT3|~190~1'
-- Equation name is '_LC6_B1', type is buried
-- synthesized logic cell
_LC6_B1 = LCELL( _EQ008);
_EQ008 = _LC3_B10 & !_LC5_B1 & !_LC8_B10;
-- Node name is '|counter24:UT3|:207'
-- Equation name is '_LC7_B1', type is buried
_LC7_B1 = DFFE( _EQ009, !_LC3_C18, GLOBAL( nCR), VCC, VCC);
_EQ009 = _LC6_B1 & _LC7_B1 & !_LC8_B1
# _LC6_B1 & !_LC7_B1 & _LC8_B1
# !EN & _LC7_B1;
-- Node name is '|counter24:UT3|:208'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = DFFE( _EQ010, !_LC3_C18, GLOBAL( nCR), VCC, VCC);
_EQ010 = _LC3_B1 & _LC4_B7 & _LC6_B1
# !_LC3_B1 & !_LC4_B7 & _LC6_B1
# !EN & _LC3_B1;
-- Node name is '|counter24:UT3|:209'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE( _EQ011, !_LC3_C18, GLOBAL( nCR), VCC, VCC);
_EQ011 = _LC3_B10 & _LC4_B1
# !EN & _LC2_B1;
-- Node name is '|counter24:UT3|:210'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( _EQ012, !_LC3_C18, GLOBAL( nCR), VCC, VCC);
_EQ012 = !_LC1_B1 & _LC3_B10
# !EN & _LC1_B1;
-- Node name is '|counter24:UT3|:261'
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = LCELL( _EQ013);
_EQ013 = _LC1_B10 & !_LC4_B10
# !_LC1_B10 & _LC4_B10 & _LC5_B1
# _LC1_B10 & !_LC5_B1
# _LC8_B10;
-- Node name is '|counter24:UT3|~273~1'
-- Equation name is '_LC6_B15', type is buried
-- synthesized logic cell
_LC6_B15 = LCELL( _EQ014);
_EQ014 = EN & !_LC7_B1
# EN & !_LC2_B1 & !_LC3_B1;
-- Node name is '|counter24:UT3|~273~2'
-- Equation name is '_LC3_B10', type is buried
-- synthesized logic cell
_LC3_B10 = LCELL( _EQ015);
_EQ015 = !_LC1_B10 & _LC2_B10 & _LC6_B15
# _LC2_B10 & _LC5_B10 & _LC6_B15;
-- Node name is '|counter24:UT3|~274~1'
-- Equation name is '_LC6_B10', type is buried
-- synthesized logic cell
_LC6_B10 = LCELL( _EQ016);
_EQ016 = _LC4_B10 & !_LC5_B1 & !_LC8_B10
# !_LC4_B10 & _LC5_B1 & !_LC8_B10;
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