📄 complete_clock.rpt
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Total output pins required: 25
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 112
Total flipflops required: 38
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 21/ 576 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 2 0 1 0 8 0 1 0 0 0 0 0 0 8 8 0 1 8 8 1 8 0 8 0 7 69/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 1 8 0 0 1 8 8 1 0 43/0
Total: 2 0 1 0 8 0 1 0 0 0 0 0 0 16 8 8 2 16 8 1 9 8 16 1 7 112/0
Device-Specific Information: f:\workhard\workhard\workhard\complete_clock.rpt
complete_clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
84 - - - -- INPUT 0 0 0 1 AdjHrkey
2 - - - -- INPUT G 0 0 0 0 AdjMinkey
1 - - - -- INPUT G 0 0 0 1 CP
43 - - - -- INPUT 0 0 0 1 CtrlBell
42 - - - -- INPUT 0 0 0 24 Mode
44 - - - -- INPUT 0 0 0 17 nCR
24 - - B -- INPUT 0 0 0 1 _1kHz
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\workhard\workhard\workhard\complete_clock.rpt
complete_clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - A -- OUTPUT 0 1 0 0 ALARM
61 - - C -- OUTPUT 0 1 0 0 LED_Hr0
27 - - C -- OUTPUT 0 1 0 0 LED_Hr1
54 - - - 21 OUTPUT 0 1 0 0 LED_Hr2
59 - - C -- OUTPUT 0 1 0 0 LED_Hr3
60 - - C -- OUTPUT 0 1 0 0 LED_Hr4
28 - - C -- OUTPUT 0 1 0 0 LED_Hr5
53 - - - 20 OUTPUT 0 1 0 0 LED_Hr6
23 - - B -- OUTPUT 0 1 0 0 LED_Hr7
51 - - - 18 OUTPUT 0 1 0 0 LED_Min0
72 - - A -- OUTPUT 0 1 0 0 LED_Min1
62 - - C -- OUTPUT 0 1 0 0 LED_Min2
58 - - C -- OUTPUT 0 1 0 0 LED_Min3
67 - - B -- OUTPUT 0 1 0 0 LED_Min4
64 - - B -- OUTPUT 0 1 0 0 LED_Min5
50 - - - 17 OUTPUT 0 1 0 0 LED_Min6
65 - - B -- OUTPUT 0 1 0 0 LED_Min7
25 - - B -- OUTPUT 0 1 0 0 LED_Sec0
35 - - - 06 OUTPUT 0 1 0 0 LED_Sec1
22 - - B -- OUTPUT 0 1 0 0 LED_Sec2
7 - - - 03 OUTPUT 0 1 0 0 LED_Sec3
52 - - - 19 OUTPUT 0 1 0 0 LED_Sec4
66 - - B -- OUTPUT 0 1 0 0 LED_Sec5
48 - - - 15 OUTPUT 0 1 0 0 LED_Sec6
21 - - B -- OUTPUT 0 1 0 0 LED_Sec7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\workhard\workhard\workhard\complete_clock.rpt
complete_clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 15 AND2 ! 0 2 0 1 |Bell:C3|counter24:SU2|:58
- 8 - C 17 AND2 s 0 4 0 3 |Bell:C3|counter24:SU2|~104~1
- 2 - C 15 OR2 ! 0 4 0 5 |Bell:C3|counter24:SU2|:104
- 6 - C 17 OR2 0 2 0 3 |Bell:C3|counter24:SU2|:142
- 5 - C 15 AND2 0 2 0 3 |Bell:C3|counter24:SU2|:149
- 3 - C 17 OR2 ! 0 4 0 4 |Bell:C3|counter24:SU2|:155
- 2 - C 17 OR2 s 0 2 0 1 |Bell:C3|counter24:SU2|~180~1
- 7 - C 17 AND2 s 0 3 0 2 |Bell:C3|counter24:SU2|~182~1
- 4 - C 17 DFFE + 0 3 0 5 |Bell:C3|counter24:SU2|:207
- 1 - C 17 DFFE + 0 2 0 6 |Bell:C3|counter24:SU2|:208
- 8 - C 21 DFFE + 0 3 0 5 |Bell:C3|counter24:SU2|:209
- 7 - C 21 DFFE + 0 1 0 5 |Bell:C3|counter24:SU2|:210
- 4 - C 15 OR2 s 0 3 0 1 |Bell:C3|counter24:SU2|~261~1
- 6 - C 15 DFFE + 0 3 0 5 |Bell:C3|counter24:SU2|:282
- 5 - C 17 DFFE + 0 3 0 4 |Bell:C3|counter24:SU2|:283
- 6 - B 14 AND2 0 2 0 1 |Bell:C3|counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 7 - B 14 AND2 0 3 0 1 |Bell:C3|counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 3 - B 14 OR2 ! 0 4 0 3 |Bell:C3|counter60:SU1|counter6:UC1|:14
- 4 - B 14 DFFE + 0 3 0 3 |Bell:C3|counter60:SU1|counter6:UC1|:41
- 5 - B 14 DFFE + 0 3 0 4 |Bell:C3|counter60:SU1|counter6:UC1|:42
- 8 - B 14 DFFE + 0 3 0 5 |Bell:C3|counter60:SU1|counter6:UC1|:43
- 2 - B 14 DFFE + 0 1 0 6 |Bell:C3|counter60:SU1|counter6:UC1|:44
- 4 - B 13 DFFE + 0 3 0 3 |Bell:C3|counter60:SU1|counter10:UC0|:41
- 8 - B 13 DFFE + 0 3 0 4 |Bell:C3|counter60:SU1|counter10:UC0|:42
- 7 - B 13 DFFE + 0 2 0 5 |Bell:C3|counter60:SU1|counter10:UC0|:43
- 6 - B 13 DFFE + 0 0 0 6 |Bell:C3|counter60:SU1|counter10:UC0|:44
- 2 - B 13 OR2 ! 0 4 0 6 |Bell:C3|counter60:SU1|:12
- 5 - B 13 OR2 s 0 4 0 1 |Bell:C3|~59~1
- 4 - B 18 OR2 s 0 4 0 1 |Bell:C3|~59~2
- 5 - B 18 OR2 s 0 4 0 1 |Bell:C3|~59~3
- 3 - B 18 AND2 s 0 3 0 1 |Bell:C3|~59~4
- 2 - C 21 OR2 s 0 4 0 1 |Bell:C3|~59~5
- 5 - B 20 AND2 s 1 3 0 1 |Bell:C3|~59~6
- 7 - C 15 OR2 s 0 4 0 1 |Bell:C3|~59~7
- 6 - C 21 OR2 s 0 4 0 1 |Bell:C3|~59~8
- 8 - C 15 OR2 s 0 4 0 1 |Bell:C3|~59~9
- 7 - B 20 OR2 s 0 4 0 1 |Bell:C3|~59~10
- 2 - B 17 AND2 s 0 4 0 1 |Radio:C2|~83~1
- 8 - C 13 AND2 0 3 0 1 |top_clock:C1|counter24:UT3|lpm_add_sub:297|addcore:adder|:59
- 1 - B 20 AND2 s 0 2 0 3 |top_clock:C1|counter24:UT3|~104~1
- 5 - C 13 AND2 s 0 4 0 2 |top_clock:C1|counter24:UT3|~104~2
- 6 - C 13 OR2 0 2 0 2 |top_clock:C1|counter24:UT3|:142
- 3 - C 22 AND2 0 3 0 4 |top_clock:C1|counter24:UT3|:149
- 4 - C 13 OR2 ! 0 4 0 4 |top_clock:C1|counter24:UT3|:155
- 6 - C 22 OR2 0 4 0 1 |top_clock:C1|counter24:UT3|:180
- 4 - C 22 AND2 s 0 3 0 2 |top_clock:C1|counter24:UT3|~190~1
- 1 - C 13 DFFE + 1 2 0 5 |top_clock:C1|counter24:UT3|:207
- 7 - C 13 DFFE + 1 2 0 6 |top_clock:C1|counter24:UT3|:208
- 5 - C 22 DFFE + 1 2 0 7 |top_clock:C1|counter24:UT3|:209
- 2 - C 20 DFFE + 1 1 0 6 |top_clock:C1|counter24:UT3|:210
- 8 - C 22 OR2 0 4 0 1 |top_clock:C1|counter24:UT3|:261
- 3 - C 13 OR2 s 0 4 0 1 |top_clock:C1|counter24:UT3|~273~1
- 2 - C 13 OR2 s 1 3 0 5 |top_clock:C1|counter24:UT3|~273~2
- 7 - C 22 OR2 s 0 3 0 1 |top_clock:C1|counter24:UT3|~274~1
- 3 - B 20 DFFE + 1 0 0 2 |top_clock:C1|counter24:UT3|:280
- 2 - B 20 DFFE + 1 0 0 2 |top_clock:C1|counter24:UT3|:281
- 1 - C 22 DFFE + 1 2 0 5 |top_clock:C1|counter24:UT3|:282
- 2 - C 22 DFFE + 1 2 0 5 |top_clock:C1|counter24:UT3|:283
- 7 - B 22 AND2 0 2 0 1 |top_clock:C1|counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 8 - B 22 AND2 0 3 0 1 |top_clock:C1|counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 5 - B 22 OR2 ! 0 4 0 5 |top_clock:C1|counter60:UT1|counter6:UC1|:14
- 1 - B 22 DFFE + 0 3 0 2 |top_clock:C1|counter60:UT1|counter6:UC1|:41
- 2 - B 22 DFFE + 0 3 0 3 |top_clock:C1|counter60:UT1|counter6:UC1|:42
- 3 - B 22 DFFE + 0 3 0 4 |top_clock:C1|counter60:UT1|counter6:UC1|:43
- 4 - B 22 DFFE + 0 1 0 5 |top_clock:C1|counter60:UT1|counter6:UC1|:44
- 5 - B 05 AND2 0 2 0 1 |top_clock:C1|counter60:UT1|counter10:UC0|lpm_add_sub:45|addcore:adder|:55
- 8 - B 05 AND2 0 3 0 1 |top_clock:C1|counter60:UT1|counter10:UC0|lpm_add_sub:45|addcore:adder|:59
- 3 - B 05 DFFE + 1 2 0 2 |top_clock:C1|counter60:UT1|counter10:UC0|:41
- 7 - B 05 DFFE + 1 2 0 3 |top_clock:C1|counter60:UT1|counter10:UC0|:42
- 4 - B 05 DFFE + 1 2 0 4 |top_clock:C1|counter60:UT1|counter10:UC0|:43
- 1 - B 01 DFFE + 1 0 0 6 |top_clock:C1|counter60:UT1|counter10:UC0|:44
- 1 - B 05 OR2 ! 0 4 0 9 |top_clock:C1|counter60:UT1|:12
- 5 - B 17 AND2 0 2 0 1 |top_clock:C1|counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 7 - B 17 AND2 0 3 0 1 |top_clock:C1|counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 3 - B 17 OR2 ! 0 4 0 4 |top_clock:C1|counter60:UT2|counter6:UC1|:14
- 4 - B 17 DFFE 0 4 0 3 |top_clock:C1|counter60:UT2|counter6:UC1|:41
- 6 - B 17 DFFE 0 4 0 4 |top_clock:C1|counter60:UT2|counter6:UC1|:42
- 8 - B 17 DFFE 0 4 0 5 |top_clock:C1|counter60:UT2|counter6:UC1|:43
- 1 - B 17 DFFE 0 2 0 6 |top_clock:C1|counter60:UT2|counter6:UC1|:44
- 7 - B 24 AND2 0 3 0 1 |top_clock:C1|counter60:UT2|counter10:UC0|lpm_add_sub:45|addcore:adder|:59
- 6 - B 24 OR2 0 3 0 1 |top_clock:C1|counter60:UT2|counter10:UC0|lpm_add_sub:45|addcore:adder|:68
- 4 - B 24 DFFE 1 3 0 3 |top_clock:C1|counter60:UT2|counter10:UC0|:41
- 2 - B 24 DFFE 1 3 0 5 |top_clock:C1|counter60:UT2|counter10:UC0|:42
- 3 - B 24 DFFE 1 3 0 5 |top_clock:C1|counter60:UT2|counter10:UC0|:43
- 5 - B 24 DFFE 1 1 0 6 |top_clock:C1|counter60:UT2|counter10:UC0|:44
- 1 - B 24 OR2 ! 0 4 0 8 |top_clock:C1|counter60:UT2|:12
- 6 - B 22 OR2 ! 2 2 0 8 |top_clock:C1|:39
- 4 - B 20 AND2 1 1 1 0 |_2to1MUX:MU1|:28
- 6 - B 20 AND2 1 1 1 0 |_2to1MUX:MU1|:32
- 3 - C 15 OR2 1 2 1 0 |_2to1MUX:MU1|:34
- 4 - C 21 OR2 1 2 1 0 |_2to1MUX:MU1|:38
- 5 - C 23 OR2 1 2 1 0 |_2to1MUX:MU1|:42
- 5 - C 21 OR2 1 2 1 0 |_2to1MUX:MU1|:46
- 1 - C 21 OR2 1 2 1 0 |_2to1MUX:MU1|:50
- 3 - C 21 OR2 1 2 1 0 |_2to1MUX:MU1|:54
- 8 - B 18 OR2 1 2 1 0 |_2to1MUX:MU2|:26
- 7 - B 18 OR2 1 2 1 0 |_2to1MUX:MU2|:30
- 6 - B 18 OR2 1 2 1 0 |_2to1MUX:MU2|:34
- 1 - B 14 OR2 1 2 1 0 |_2to1MUX:MU2|:38
- 6 - C 16 OR2 1 2 1 0 |_2to1MUX:MU2|:42
- 1 - B 13 OR2 1 2 1 0 |_2to1MUX:MU2|:46
- 3 - B 13 OR2 1 2 1 0 |_2to1MUX:MU2|:50
- 1 - B 18 OR2 1 2 1 0 |_2to1MUX:MU2|:54
- 1 - B 07 AND2 1 1 1 0 |_2to1MUX:MU3|:28
- 4 - B 16 AND2 1 1 1 0 |_2to1MUX:MU3|:32
- 2 - B 18 AND2 1 1 1 0 |_2to1MUX:MU3|:36
- 8 - B 19 AND2 1 1 1 0 |_2to1MUX:MU3|:40
- 1 - B 03 AND2 1 1 1 0 |_2to1MUX:MU3|:44
- 2 - B 05 AND2 1 1 1 0 |_2to1MUX:MU3|:48
- 6 - B 05 AND2 1 1 1 0 |_2to1MUX:MU3|:52
- 8 - B 01 AND2 1 1 1 0 |_2to1MUX:MU3|:56
- 8 - B 20 OR2 1 3 1 0 :35
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\workhard\workhard\workhard\complete_clock.rpt
complete_clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 7/ 96( 7%) 4/ 48( 8%) 26/ 48( 54%) 1/16( 6%) 8/16( 50%) 0/16( 0%)
C: 6/ 96( 6%) 0/ 48( 0%) 26/ 48( 54%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
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