📄 complete_clock.rpt
字号:
- 3 - A 21 OR2 1 2 1 0 |_2to1MUX:MU1|:34
- 2 - A 19 OR2 1 2 1 0 |_2to1MUX:MU1|:38
- 1 - A 19 OR2 1 2 1 0 |_2to1MUX:MU1|:42
- 4 - A 17 OR2 1 2 1 0 |_2to1MUX:MU1|:46
- 1 - A 17 OR2 1 2 1 0 |_2to1MUX:MU1|:50
- 4 - C 15 OR2 1 2 1 0 |_2to1MUX:MU1|:54
- 4 - C 16 OR2 1 2 1 0 |_2to1MUX:MU2|:26
- 1 - C 13 OR2 1 2 1 0 |_2to1MUX:MU2|:30
- 1 - C 11 OR2 1 2 1 0 |_2to1MUX:MU2|:34
- 2 - C 09 OR2 1 2 1 0 |_2to1MUX:MU2|:38
- 2 - C 10 OR2 1 2 1 0 |_2to1MUX:MU2|:42
- 8 - C 08 OR2 1 2 1 0 |_2to1MUX:MU2|:46
- 2 - C 06 OR2 1 2 1 0 |_2to1MUX:MU2|:50
- 6 - C 06 OR2 1 2 1 0 |_2to1MUX:MU2|:54
- 5 - C 01 AND2 1 1 1 0 |_2to1MUX:MU3|:28
- 2 - C 02 AND2 1 1 1 0 |_2to1MUX:MU3|:32
- 1 - A 07 AND2 1 1 1 0 |_2to1MUX:MU3|:36
- 8 - A 07 AND2 1 1 1 0 |_2to1MUX:MU3|:40
- 6 - B 01 AND2 1 1 1 0 |_2to1MUX:MU3|:44
- 4 - A 03 AND2 1 1 1 0 |_2to1MUX:MU3|:48
- 2 - A 07 AND2 1 1 1 0 |_2to1MUX:MU3|:52
- 1 - C 01 AND2 1 1 1 0 |_2to1MUX:MU3|:56
- 2 - C 13 OR2 0 4 1 0 :36
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\workhard\complete_clock.rpt
complete_clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 13/ 96( 13%) 22/ 48( 45%) 10/ 48( 20%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 26/ 96( 27%) 24/ 48( 50%) 3/ 48( 6%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 6/24( 25%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\workhard\complete_clock.rpt
complete_clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 CP
LCELL 8 |top_clock:UC1|:38
LCELL 6 |top_clock:UC1|:63
INPUT 3 _1kHz
Device-Specific Information: f:\workhard\complete_clock.rpt
complete_clock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 22 nCR
Device-Specific Information: f:\workhard\complete_clock.rpt
complete_clock
** EQUATIONS **
AdjHrkey : INPUT;
AdjMinkey : INPUT;
CP : INPUT;
CtrlBell : INPUT;
Mode : INPUT;
nCR : INPUT;
_1kHz : INPUT;
-- Node name is 'ALARM'
-- Equation name is 'ALARM', type is output
ALARM = _LC2_C13;
-- Node name is 'LED_Hr0'
-- Equation name is 'LED_Hr0', type is output
LED_Hr0 = _LC4_C15;
-- Node name is 'LED_Hr1'
-- Equation name is 'LED_Hr1', type is output
LED_Hr1 = _LC1_A17;
-- Node name is 'LED_Hr2'
-- Equation name is 'LED_Hr2', type is output
LED_Hr2 = _LC4_A17;
-- Node name is 'LED_Hr3'
-- Equation name is 'LED_Hr3', type is output
LED_Hr3 = _LC1_A19;
-- Node name is 'LED_Hr4'
-- Equation name is 'LED_Hr4', type is output
LED_Hr4 = _LC2_A19;
-- Node name is 'LED_Hr5'
-- Equation name is 'LED_Hr5', type is output
LED_Hr5 = _LC3_A21;
-- Node name is 'LED_Hr6'
-- Equation name is 'LED_Hr6', type is output
LED_Hr6 = GND;
-- Node name is 'LED_Hr7'
-- Equation name is 'LED_Hr7', type is output
LED_Hr7 = GND;
-- Node name is 'LED_Min0'
-- Equation name is 'LED_Min0', type is output
LED_Min0 = _LC6_C6;
-- Node name is 'LED_Min1'
-- Equation name is 'LED_Min1', type is output
LED_Min1 = _LC2_C6;
-- Node name is 'LED_Min2'
-- Equation name is 'LED_Min2', type is output
LED_Min2 = _LC8_C8;
-- Node name is 'LED_Min3'
-- Equation name is 'LED_Min3', type is output
LED_Min3 = _LC2_C10;
-- Node name is 'LED_Min4'
-- Equation name is 'LED_Min4', type is output
LED_Min4 = _LC2_C9;
-- Node name is 'LED_Min5'
-- Equation name is 'LED_Min5', type is output
LED_Min5 = _LC1_C11;
-- Node name is 'LED_Min6'
-- Equation name is 'LED_Min6', type is output
LED_Min6 = _LC1_C13;
-- Node name is 'LED_Min7'
-- Equation name is 'LED_Min7', type is output
LED_Min7 = _LC4_C16;
-- Node name is 'LED_Sec0'
-- Equation name is 'LED_Sec0', type is output
LED_Sec0 = _LC1_C1;
-- Node name is 'LED_Sec1'
-- Equation name is 'LED_Sec1', type is output
LED_Sec1 = _LC2_A7;
-- Node name is 'LED_Sec2'
-- Equation name is 'LED_Sec2', type is output
LED_Sec2 = _LC4_A3;
-- Node name is 'LED_Sec3'
-- Equation name is 'LED_Sec3', type is output
LED_Sec3 = _LC6_B1;
-- Node name is 'LED_Sec4'
-- Equation name is 'LED_Sec4', type is output
LED_Sec4 = _LC8_A7;
-- Node name is 'LED_Sec5'
-- Equation name is 'LED_Sec5', type is output
LED_Sec5 = _LC1_A7;
-- Node name is 'LED_Sec6'
-- Equation name is 'LED_Sec6', type is output
LED_Sec6 = _LC2_C2;
-- Node name is 'LED_Sec7'
-- Equation name is 'LED_Sec7', type is output
LED_Sec7 = _LC5_C1;
-- Node name is '|BaoShi:UC4|~80~1'
-- Equation name is '_LC4_A12', type is buried
-- synthesized logic cell
_LC4_A12 = LCELL( _EQ001);
_EQ001 = !_LC1_A10 & _LC4_A10 & !_LC5_A4 & !_LC5_A6;
-- Node name is '|BaoShi:UC4|~99~1'
-- Equation name is '_LC8_A6', type is buried
-- synthesized logic cell
!_LC8_A6 = _LC8_A6~NOT;
_LC8_A6~NOT = LCELL( _EQ002);
_EQ002 = !_LC2_A10 & !_LC7_A10;
-- Node name is '|BaoShi:UC4|~99~2'
-- Equation name is '_LC2_A6', type is buried
-- synthesized logic cell
!_LC2_A6 = _LC2_A6~NOT;
_LC2_A6~NOT = LCELL( _EQ003);
_EQ003 = _LC1_A10 & _LC3_A10 & !_LC8_A6 & !_LC8_A10
# !_LC1_A10 & !_LC3_A10 & !_LC8_A6 & _LC8_A10;
-- Node name is '|BaoShi:UC4|:161'
-- Equation name is '_LC7_A12', type is buried
_LC7_A12 = LCELL( _EQ004);
_EQ004 = !_LC2_A6 & _LC4_A10;
-- Node name is '|BaoShi:UC4|:223'
-- Equation name is '_LC6_A12', type is buried
_LC6_A12 = LCELL( _EQ005);
_EQ005 = _LC1_A10 & !_LC4_A10 & !_LC5_A6;
-- Node name is '|BaoShi:UC4|:285'
-- Equation name is '_LC3_A12', type is buried
_LC3_A12 = LCELL( _EQ006);
_EQ006 = _LC1_A10 & _LC4_A10 & !_LC5_A6;
-- Node name is '|BaoShi:UC4|~347~1'
-- Equation name is '_LC3_A6', type is buried
-- synthesized logic cell
!_LC3_A6 = _LC3_A6~NOT;
_LC3_A6~NOT = LCELL( _EQ007);
_EQ007 = !_LC1_A10 & _LC2_A10 & _LC3_A10 & !_LC8_A10
# _LC1_A10 & !_LC2_A10 & !_LC3_A10 & _LC8_A10;
-- Node name is '|BaoShi:UC4|~347~2'
-- Equation name is '_LC1_A6', type is buried
-- synthesized logic cell
!_LC1_A6 = _LC1_A6~NOT;
_LC1_A6~NOT = LCELL( _EQ008);
_EQ008 = !_LC3_A6 & !_LC7_A10;
-- Node name is '|BaoShi:UC4|:363'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ009);
_EQ009 = !_LC2_A4
# _LC4_A4 & !_LC5_A4;
-- Node name is '|BaoShi:UC4|:409'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ010);
_EQ010 = !_LC3_A6 & _LC4_A10 & !_LC7_A10;
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