📄 complete_clock.rpt
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** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 12/22( 54%)
A3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
A4 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 1/2 1/2 2/22( 9%)
A6 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
A7 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 10/22( 45%)
A9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
A10 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 1/2 7/22( 31%)
A12 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
A16 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 0/2 4/22( 18%)
A17 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
A19 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
A20 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A21 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
B1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C1 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
C2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
C4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C5 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
C6 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 7/22( 31%)
C8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C10 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
C11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C12 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
C13 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 19/22( 86%)
C15 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 32/53 ( 60%)
Total logic cells used: 141/576 ( 24%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.21/4 ( 80%)
Total fan-in: 453/2304 ( 19%)
Total input pins required: 7
Total input I/O cell registers required: 0
Total output pins required: 25
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 141
Total flipflops required: 37
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 42/ 576 ( 7%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 7 0 1 8 0 8 8 0 8 8 0 8 0 0 0 0 8 2 0 3 1 8 0 0 0 78/0
B: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
C: 8 1 8 1 8 8 0 1 1 7 1 8 0 8 0 1 1 0 0 0 0 0 0 0 0 62/0
Total: 16 1 9 9 8 16 8 1 9 15 1 16 0 8 0 1 9 2 0 3 1 8 0 0 0 141/0
Device-Specific Information: f:\workhard\complete_clock.rpt
complete_clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - - 02 INPUT 0 0 0 1 AdjHrkey
8 - - - 03 INPUT 0 0 0 1 AdjMinkey
3 - - - 12 INPUT 0 0 0 24 CP
10 - - - 01 INPUT 0 0 0 1 CtrlBell
11 - - - 01 INPUT 0 0 0 22 Mode
16 - - A -- INPUT 0 0 0 22 nCR
6 - - - 04 INPUT 0 0 0 3 _1kHz
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\workhard\complete_clock.rpt
complete_clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - - 13 OUTPUT 0 1 0 0 ALARM
49 - - - 16 OUTPUT 0 1 0 0 LED_Hr0
50 - - - 17 OUTPUT 0 1 0 0 LED_Hr1
51 - - - 18 OUTPUT 0 1 0 0 LED_Hr2
52 - - - 19 OUTPUT 0 1 0 0 LED_Hr3
53 - - - 20 OUTPUT 0 1 0 0 LED_Hr4
54 - - - 21 OUTPUT 0 1 0 0 LED_Hr5
58 - - C -- OUTPUT 0 0 0 0 LED_Hr6
59 - - C -- OUTPUT 0 0 0 0 LED_Hr7
30 - - C -- OUTPUT 0 1 0 0 LED_Min0
35 - - - 06 OUTPUT 0 1 0 0 LED_Min1
36 - - - 07 OUTPUT 0 1 0 0 LED_Min2
37 - - - 09 OUTPUT 0 1 0 0 LED_Min3
38 - - - 10 OUTPUT 0 1 0 0 LED_Min4
39 - - - 11 OUTPUT 0 1 0 0 LED_Min5
47 - - - 14 OUTPUT 0 1 0 0 LED_Min6
48 - - - 15 OUTPUT 0 1 0 0 LED_Min7
21 - - B -- OUTPUT 0 1 0 0 LED_Sec0
22 - - B -- OUTPUT 0 1 0 0 LED_Sec1
23 - - B -- OUTPUT 0 1 0 0 LED_Sec2
24 - - B -- OUTPUT 0 1 0 0 LED_Sec3
25 - - B -- OUTPUT 0 1 0 0 LED_Sec4
27 - - C -- OUTPUT 0 1 0 0 LED_Sec5
28 - - C -- OUTPUT 0 1 0 0 LED_Sec6
29 - - C -- OUTPUT 0 1 0 0 LED_Sec7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\workhard\complete_clock.rpt
complete_clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 12 AND2 s 0 4 0 1 |BaoShi:UC4|~80~1
- 8 - A 06 AND2 s ! 0 2 0 1 |BaoShi:UC4|~99~1
- 2 - A 06 OR2 s ! 0 4 0 3 |BaoShi:UC4|~99~2
- 7 - A 12 AND2 0 2 0 1 |BaoShi:UC4|:161
- 6 - A 12 AND2 0 3 0 1 |BaoShi:UC4|:223
- 3 - A 12 AND2 0 3 0 1 |BaoShi:UC4|:285
- 3 - A 06 OR2 s ! 0 4 0 3 |BaoShi:UC4|~347~1
- 1 - A 06 AND2 s ! 0 2 0 1 |BaoShi:UC4|~347~2
- 3 - A 01 OR2 0 3 0 1 |BaoShi:UC4|:363
- 2 - A 01 AND2 0 3 0 1 |BaoShi:UC4|:409
- 4 - A 04 AND2 0 2 0 4 |BaoShi:UC4|:427
- 6 - A 04 OR2 0 4 0 1 |BaoShi:UC4|:487
- 5 - A 09 OR2 s ! 0 4 0 3 |BaoShi:UC4|~533~1
- 7 - A 01 OR2 s 0 4 0 1 |BaoShi:UC4|~576~1
- 1 - A 09 AND2 s ! 0 2 0 3 |BaoShi:UC4|~595~1
- 6 - A 09 OR2 s ! 0 4 0 3 |BaoShi:UC4|~595~2
- 4 - A 07 AND2 0 3 0 1 |BaoShi:UC4|:670
- 5 - A 07 OR2 s 0 4 0 1 |BaoShi:UC4|~700~1
- 5 - A 06 OR2 s ! 0 4 0 5 |BaoShi:UC4|~719~1
- 6 - A 07 OR2 0 3 0 1 |BaoShi:UC4|:730
- 7 - A 07 AND2 s 0 4 0 1 |BaoShi:UC4|~762~1
- 6 - A 06 AND2 s 0 2 0 1 |BaoShi:UC4|~775~1
- 7 - A 06 OR2 s 0 3 0 1 |BaoShi:UC4|~775~2
- 4 - A 06 AND2 s 0 3 0 1 |BaoShi:UC4|~775~3
- 4 - C 01 AND2 s 0 4 0 1 |BaoShi:UC4|~776~1
- 4 - A 01 OR2 s 0 4 0 1 |BaoShi:UC4|~776~2
- 5 - A 01 OR2 s 0 4 0 1 |BaoShi:UC4|~776~3
- 6 - A 01 OR2 s 0 4 0 1 |BaoShi:UC4|~776~4
- 5 - A 12 OR2 s 0 4 0 1 |BaoShi:UC4|~776~5
- 8 - A 12 OR2 s 0 4 0 1 |BaoShi:UC4|~776~6
- 1 - A 12 OR2 s 0 4 0 1 |BaoShi:UC4|~776~7
- 1 - A 01 OR2 s 0 4 0 1 |BaoShi:UC4|~776~8
- 3 - A 07 OR2 s 0 4 0 1 |BaoShi:UC4|~776~9
- 6 - C 01 OR2 0 3 0 1 |BaoShi:UC4|:776
- 8 - A 16 AND2 0 3 0 1 |Bell:UC3|counter24:SU2|lpm_add_sub:297|addcore:adder|:59
- 3 - A 16 OR2 s 0 3 0 1 |Bell:UC3|counter24:SU2|~104~1
- 4 - A 21 OR2 ! 0 4 0 6 |Bell:UC3|counter24:SU2|:104
- 1 - A 16 OR2 0 4 0 2 |Bell:UC3|counter24:SU2|:134
- 6 - A 16 AND2 ! 0 2 0 1 |Bell:UC3|counter24:SU2|:142
- 5 - A 21 AND2 0 3 0 3 |Bell:UC3|counter24:SU2|:150
- 4 - A 16 OR2 ! 0 4 0 3 |Bell:UC3|counter24:SU2|:156
- 2 - A 21 OR2 s 0 2 0 3 |Bell:UC3|counter24:SU2|~181~1
- 5 - A 16 DFFE 1 3 0 5 |Bell:UC3|counter24:SU2|:208
- 2 - A 16 DFFE 1 3 0 6 |Bell:UC3|counter24:SU2|:209
- 7 - A 16 DFFE 1 3 0 7 |Bell:UC3|counter24:SU2|:210
- 1 - A 20 DFFE 1 1 0 7 |Bell:UC3|counter24:SU2|:211
- 7 - A 21 OR2 s 0 3 0 1 |Bell:UC3|counter24:SU2|~262~1
- 8 - A 21 DFFE 1 3 0 5 |Bell:UC3|counter24:SU2|:283
- 1 - A 21 DFFE 1 3 0 5 |Bell:UC3|counter24:SU2|:284
- 7 - C 12 AND2 0 2 0 1 |Bell:UC3|counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 8 - C 12 AND2 0 3 0 1 |Bell:UC3|counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 6 - C 12 OR2 ! 0 4 0 3 |Bell:UC3|counter60:SU1|counter6:UC1|:14
- 2 - C 12 DFFE 1 3 0 3 |Bell:UC3|counter60:SU1|counter6:UC1|:41
- 5 - C 12 DFFE 1 3 0 4 |Bell:UC3|counter60:SU1|counter6:UC1|:42
- 4 - C 12 DFFE 1 3 0 5 |Bell:UC3|counter60:SU1|counter6:UC1|:43
- 1 - C 12 DFFE 1 1 0 6 |Bell:UC3|counter60:SU1|counter6:UC1|:44
- 5 - C 10 DFFE 1 3 0 3 |Bell:UC3|counter60:SU1|counter10:UC0|:41
- 3 - C 10 DFFE 1 3 0 4 |Bell:UC3|counter60:SU1|counter10:UC0|:42
- 4 - C 10 DFFE 1 2 0 5 |Bell:UC3|counter60:SU1|counter10:UC0|:43
- 1 - C 10 DFFE 1 0 0 6 |Bell:UC3|counter60:SU1|counter10:UC0|:44
- 7 - C 10 OR2 ! 0 4 0 6 |Bell:UC3|counter60:SU1|:12
- 2 - C 01 OR2 1 2 0 1 |Bell:UC3|:56
- 3 - A 19 OR2 s 0 4 0 1 |Bell:UC3|~59~1
- 6 - A 21 OR2 s 0 4 0 1 |Bell:UC3|~59~2
- 6 - C 10 OR2 s 1 3 0 1 |Bell:UC3|~59~3
- 3 - C 13 OR2 s 0 3 0 1 |Bell:UC3|~59~4
- 4 - C 13 OR2 s 0 4 0 1 |Bell:UC3|~59~5
- 5 - C 13 OR2 s 0 4 0 1 |Bell:UC3|~59~6
- 3 - C 12 OR2 s 0 4 0 1 |Bell:UC3|~59~7
- 8 - C 06 OR2 s 0 4 0 1 |Bell:UC3|~59~8
- 6 - C 13 OR2 s 0 4 0 1 |Bell:UC3|~59~9
- 7 - C 13 AND2 0 4 0 1 |Bell:UC3|:59
- 3 - C 01 DFFE 1 0 0 3 |Divided_Frequency:UC0|:5
- 8 - C 01 AND2 s 0 3 0 1 |Radio:UC2|~68~1
- 4 - C 05 OR2 s ! 0 2 0 1 |Radio:UC2|~78~1
- 7 - C 01 OR2 1 3 0 1 |Radio:UC2|:82
- 2 - A 12 AND2 0 3 0 1 |top_clock:UC1|counter24:UT3|lpm_add_sub:297|addcore:adder|:59
- 3 - A 09 AND2 ! 0 2 0 3 |top_clock:UC1|counter24:UT3|:58
- 7 - A 09 AND2 s 0 3 0 1 |top_clock:UC1|counter24:UT3|~104~1
- 4 - A 09 OR2 ! 0 4 0 6 |top_clock:UC1|counter24:UT3|:104
- 8 - C 13 OR2 0 2 0 3 |top_clock:UC1|counter24:UT3|:142
- 8 - A 09 OR2 0 4 0 3 |top_clock:UC1|counter24:UT3|:150
- 2 - A 09 OR2 ! 0 3 0 3 |top_clock:UC1|counter24:UT3|:156
- 5 - A 10 OR2 s 0 2 0 3 |top_clock:UC1|counter24:UT3|~181~1
- 2 - A 10 DFFE 1 4 0 9 |top_clock:UC1|counter24:UT3|:208
- 1 - A 10 DFFE 1 4 0 11 |top_clock:UC1|counter24:UT3|:209
- 8 - A 10 DFFE 1 4 0 9 |top_clock:UC1|counter24:UT3|:210
- 4 - A 10 DFFE 1 2 0 17 |top_clock:UC1|counter24:UT3|:211
- 6 - A 10 OR2 s 0 3 0 1 |top_clock:UC1|counter24:UT3|~262~1
- 7 - A 10 DFFE 1 4 0 12 |top_clock:UC1|counter24:UT3|:283
- 3 - A 10 DFFE 1 4 0 10 |top_clock:UC1|counter24:UT3|:284
- 2 - C 05 AND2 0 2 0 1 |top_clock:UC1|counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 5 - C 05 AND2 0 3 0 1 |top_clock:UC1|counter60:UT1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 7 - C 05 OR2 ! 0 4 0 6 |top_clock:UC1|counter60:UT1|counter6:UC1|:14
- 8 - C 05 DFFE 2 3 0 3 |top_clock:UC1|counter60:UT1|counter6:UC1|:41
- 1 - C 05 DFFE 2 3 0 4 |top_clock:UC1|counter60:UT1|counter6:UC1|:42
- 6 - C 05 DFFE 2 3 0 7 |top_clock:UC1|counter60:UT1|counter6:UC1|:43
- 2 - A 04 DFFE 2 1 0 12 |top_clock:UC1|counter60:UT1|counter6:UC1|:44
- 8 - A 04 DFFE 2 3 0 7 |top_clock:UC1|counter60:UT1|counter10:UC0|:41
- 3 - A 04 DFFE 2 3 0 7 |top_clock:UC1|counter60:UT1|counter10:UC0|:42
- 5 - A 04 DFFE 2 2 0 9 |top_clock:UC1|counter60:UT1|counter10:UC0|:43
- 7 - A 04 DFFE 2 0 0 8 |top_clock:UC1|counter60:UT1|counter10:UC0|:44
- 1 - A 04 OR2 ! 0 4 0 9 |top_clock:UC1|counter60:UT1|:12
- 5 - C 03 AND2 0 2 0 1 |top_clock:UC1|counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 8 - C 03 AND2 0 3 0 1 |top_clock:UC1|counter60:UT2|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 1 - C 03 OR2 ! 0 4 0 4 |top_clock:UC1|counter60:UT2|counter6:UC1|:14
- 2 - C 03 DFFE 1 4 0 3 |top_clock:UC1|counter60:UT2|counter6:UC1|:41
- 7 - C 03 DFFE 1 4 0 4 |top_clock:UC1|counter60:UT2|counter6:UC1|:42
- 4 - C 03 DFFE 1 4 0 5 |top_clock:UC1|counter60:UT2|counter6:UC1|:43
- 3 - C 03 DFFE 1 2 0 6 |top_clock:UC1|counter60:UT2|counter6:UC1|:44
- 3 - C 06 DFFE 1 4 0 3 |top_clock:UC1|counter60:UT2|counter10:UC0|:41
- 7 - C 06 DFFE 1 4 0 4 |top_clock:UC1|counter60:UT2|counter10:UC0|:42
- 4 - C 06 DFFE 1 3 0 5 |top_clock:UC1|counter60:UT2|counter10:UC0|:43
- 5 - C 06 DFFE 1 1 0 6 |top_clock:UC1|counter60:UT2|counter10:UC0|:44
- 1 - C 06 OR2 ! 0 4 0 7 |top_clock:UC1|counter60:UT2|:12
- 3 - C 05 OR2 ! 2 2 0 8 |top_clock:UC1|:38
- 4 - C 04 OR2 ! 2 2 0 6 |top_clock:UC1|:63
- 6 - C 03 OR2 s 0 2 0 2 |top_clock:UC1|~65~1
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