baoshi.rpt

数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能

-- Equation name is '_LC6_B2', type is buried 
_LC6_B2  = LCELL( _EQ016);
  _EQ016 = !second1 & !second3
         # !second2 & !second3
         # !second4;

-- Node name is '~593~1' 
-- Equation name is '~593~1', location is LC2_B2, type is buried.
-- synthesized logic cell 
_LC2_B2  = LCELL( _EQ017);
  _EQ017 =  hour0 & !_LC6_B3 & !second4
         #  hour0 & !_LC6_B3 & !second3;

-- Node name is '~612~1' 
-- Equation name is '~612~1', location is LC4_B3, type is buried.
-- synthesized logic cell 
!_LC4_B3 = _LC4_B3~NOT;
_LC4_B3~NOT = LCELL( _EQ018);
  _EQ018 =  hour1 & !hour2 & !hour4 &  hour5
         # !hour1 & !hour2 &  hour4 & !hour5;

-- Node name is '~612~2' 
-- Equation name is '~612~2', location is LC1_B10, type is buried.
-- synthesized logic cell 
!_LC1_B10 = _LC1_B10~NOT;
_LC1_B10~NOT = LCELL( _EQ019);
  _EQ019 = !_LC2_B3 & !_LC4_B3;

-- Node name is ':687' 
-- Equation name is '_LC2_B11', type is buried 
_LC2_B11 = LCELL( _EQ020);
  _EQ020 =  _LC2_B7 & !second1 & !second4;

-- Node name is '~717~1' 
-- Equation name is '~717~1', location is LC3_B11, type is buried.
-- synthesized logic cell 
_LC3_B11 = LCELL( _EQ021);
  _EQ021 =  hour0 & !_LC1_B10 &  _LC2_B11
         #  hour0 & !_LC1_B10 & !second5;

-- Node name is '~736~1' 
-- Equation name is '~736~1', location is LC2_B3, type is buried.
-- synthesized logic cell 
!_LC2_B3 = _LC2_B3~NOT;
_LC2_B3~NOT = LCELL( _EQ022);
  _EQ022 = !hour3 & !hour6 & !hour7;

-- Node name is '~736~2' 
-- Equation name is '~736~2', location is LC1_B3, type is buried.
-- synthesized logic cell 
!_LC1_B3 = _LC1_B3~NOT;
_LC1_B3~NOT = LCELL( _EQ023);
  _EQ023 = !hour1 & !hour4 & !hour5 & !_LC2_B3
         #  hour1 &  hour4 & !hour5 & !_LC2_B3;

-- Node name is ':747' 
-- Equation name is '_LC4_B11', type is buried 
_LC4_B11 = LCELL( _EQ024);
  _EQ024 = !second5
         #  _LC2_B7 & !second4;

-- Node name is '~779~1' 
-- Equation name is '~779~1', location is LC5_B11, type is buried.
-- synthesized logic cell 
_LC5_B11 = LCELL( _EQ025);
  _EQ025 = !hour0 & !hour2 & !_LC1_B3 &  _LC4_B11;

-- Node name is '~792~1' 
-- Equation name is '~792~1', location is LC2_B8, type is buried.
-- synthesized logic cell 
_LC2_B8  = LCELL( _EQ026);
  _EQ026 =  _LC1_B3 &  _LC6_B3;

-- Node name is '~792~2' 
-- Equation name is '~792~2', location is LC2_B9, type is buried.
-- synthesized logic cell 
_LC2_B9  = LCELL( _EQ027);
  _EQ027 =  _LC1_B9 &  _LC4_B3
         #  _LC1_B9 &  _LC2_B3;

-- Node name is '~792~3' 
-- Equation name is '~792~3', location is LC1_B8, type is buried.
-- synthesized logic cell 
_LC1_B8  = LCELL( _EQ028);
  _EQ028 =  _LC2_B8 &  _LC2_B9 &  _LC5_B3;

-- Node name is '~793~1' 
-- Equation name is '~793~1', location is LC1_B11, type is buried.
-- synthesized logic cell 
_LC1_B11 = LCELL( _EQ029);
  _EQ029 =  hz1k &  second0 & !second6 & !second7;

-- Node name is '~793~2' 
-- Equation name is '~793~2', location is LC4_B9, type is buried.
-- synthesized logic cell 
_LC4_B9  = LCELL( _EQ030);
  _EQ030 = !hour0 & !_LC1_B9 & !second2
         #  _LC3_B9 & !second2;

-- Node name is '~793~3' 
-- Equation name is '~793~3', location is LC8_B9, type is buried.
-- synthesized logic cell 
_LC8_B9  = LCELL( _EQ031);
  _EQ031 =  _LC4_B9 & !second3
         #  _LC6_B9 & !second3
         #  _LC7_B9 & !second3;

-- Node name is '~793~4' 
-- Equation name is '~793~4', location is LC5_B9, type is buried.
-- synthesized logic cell 
_LC5_B9  = LCELL( _EQ032);
  _EQ032 =  hour0 &  hour2 & !_LC1_B3
         #  _LC8_B9;

-- Node name is '~793~5' 
-- Equation name is '~793~5', location is LC7_B2, type is buried.
-- synthesized logic cell 
_LC7_B2  = LCELL( _EQ033);
  _EQ033 =  _LC5_B2
         # !hour0 &  _LC6_B2 & !_LC6_B3;

-- Node name is '~793~6' 
-- Equation name is '~793~6', location is LC8_B2, type is buried.
-- synthesized logic cell 
_LC8_B2  = LCELL( _EQ034);
  _EQ034 =  _LC3_B2
         # !hour0 & !_LC1_B10
         #  _LC7_B2;

-- Node name is '~793~7' 
-- Equation name is '~793~7', location is LC1_B2, type is buried.
-- synthesized logic cell 
_LC1_B2  = LCELL( _EQ035);
  _EQ035 =  _LC5_B9 & !second4
         #  _LC2_B2
         #  _LC8_B2;

-- Node name is '~793~8' 
-- Equation name is '~793~8', location is LC6_B11, type is buried.
-- synthesized logic cell 
_LC6_B11 = LCELL( _EQ036);
  _EQ036 =  _LC1_B2 & !second5
         #  _LC3_B11
         #  _LC5_B11;

-- Node name is ':793' 
-- Equation name is '_LC7_B11', type is buried 
_LC7_B11 = LCELL( _EQ037);
  _EQ037 =  _LC1_B8 &  _LC8_B11
         #  _LC1_B11 &  _LC6_B11;

-- Node name is ':799' 
-- Equation name is '_LC8_B11', type is buried 
_LC8_B11 = LCELL( _EQ038);
  _EQ038 =  _LC1_A3 &  _LC1_C11 &  _LC7_B11
         # !_LC1_A3 &  _LC8_B11
         # !_LC1_C11 &  _LC8_B11;



Project Information                                     g:\workhard\baoshi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,875K