📄 counter60.rpt
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Device-Specific Information: f:\workhard\counter60.rpt
counter60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 1/ 96( 1%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\workhard\counter60.rpt
counter60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CP
Device-Specific Information: f:\workhard\counter60.rpt
counter60
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 nCR
Device-Specific Information: f:\workhard\counter60.rpt
counter60
** EQUATIONS **
CP : INPUT;
EN : INPUT;
nCR : INPUT;
-- Node name is 'Cnt0'
-- Equation name is 'Cnt0', type is output
Cnt0 = _LC1_C11;
-- Node name is 'Cnt1'
-- Equation name is 'Cnt1', type is output
Cnt1 = _LC7_C11;
-- Node name is 'Cnt2'
-- Equation name is 'Cnt2', type is output
Cnt2 = _LC3_C11;
-- Node name is 'Cnt3'
-- Equation name is 'Cnt3', type is output
Cnt3 = _LC2_C11;
-- Node name is 'Cnt4'
-- Equation name is 'Cnt4', type is output
Cnt4 = _LC8_C11;
-- Node name is 'Cnt5'
-- Equation name is 'Cnt5', type is output
Cnt5 = _LC1_B6;
-- Node name is 'Cnt6'
-- Equation name is 'Cnt6', type is output
Cnt6 = _LC4_B6;
-- Node name is 'Cnt7'
-- Equation name is 'Cnt7', type is output
Cnt7 = _LC6_B6;
-- Node name is '|counter6:UC1|lpm_add_sub:45|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = LCELL( _EQ001);
_EQ001 = _LC1_B6 & _LC8_C11;
-- Node name is '|counter6:UC1|lpm_add_sub:45|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = LCELL( _EQ002);
_EQ002 = _LC1_B6 & _LC4_B6 & _LC8_C11;
-- Node name is '|counter6:UC1|:14'
-- Equation name is '_LC2_B6', type is buried
!_LC2_B6 = _LC2_B6~NOT;
_LC2_B6~NOT = LCELL( _EQ003);
_EQ003 = !_LC4_B6
# _LC1_B6
# _LC6_B6
# !_LC8_C11;
-- Node name is '|counter6:UC1|:41'
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = DFFE( _EQ004, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ004 = !_LC5_C11 & _LC6_B6
# !_LC2_B6 & !_LC5_B6 & _LC6_B6
# !_LC2_B6 & _LC5_B6 & _LC5_C11 & !_LC6_B6;
-- Node name is '|counter6:UC1|:42'
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = DFFE( _EQ005, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ005 = _LC4_B6 & !_LC5_C11
# !_LC2_B6 & !_LC3_B6 & _LC4_B6
# !_LC2_B6 & _LC3_B6 & !_LC4_B6 & _LC5_C11;
-- Node name is '|counter6:UC1|:43'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = DFFE( _EQ006, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ006 = _LC1_B6 & !_LC5_C11
# _LC1_B6 & !_LC2_B6 & !_LC8_C11
# !_LC1_B6 & !_LC2_B6 & _LC5_C11 & _LC8_C11;
-- Node name is '|counter6:UC1|:44'
-- Equation name is '_LC8_C11', type is buried
_LC8_C11 = DFFE( _EQ007, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ007 = _LC5_C11 & !_LC8_C11
# !_LC5_C11 & _LC8_C11;
-- Node name is '|counter10:UC0|lpm_add_sub:45|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C11', type is buried
_LC6_C11 = LCELL( _EQ008);
_EQ008 = _LC1_C11 & _LC3_C11 & _LC7_C11;
-- Node name is '|counter10:UC0|lpm_add_sub:45|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_C11', type is buried
_LC4_C11 = LCELL( _EQ009);
_EQ009 = _LC3_C11 & !_LC7_C11
# !_LC1_C11 & _LC3_C11
# _LC1_C11 & !_LC3_C11 & _LC7_C11;
-- Node name is '|counter10:UC0|:41'
-- Equation name is '_LC2_C11', type is buried
_LC2_C11 = DFFE( _EQ010, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ010 = _LC2_C11 & !_LC5_C11 & !_LC6_C11
# EN & !_LC2_C11 & !_LC5_C11 & _LC6_C11
# !EN & _LC2_C11;
-- Node name is '|counter10:UC0|:42'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = DFFE( _EQ011, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ011 = EN & _LC4_C11 & !_LC5_C11
# !EN & _LC3_C11;
-- Node name is '|counter10:UC0|:43'
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = DFFE( _EQ012, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ012 = !_LC1_C11 & !_LC5_C11 & _LC7_C11
# EN & _LC1_C11 & !_LC5_C11 & !_LC7_C11
# !EN & _LC7_C11;
-- Node name is '|counter10:UC0|:44'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = DFFE( _EQ013, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ013 = EN & !_LC1_C11
# !EN & _LC1_C11;
-- Node name is ':12'
-- Equation name is '_LC5_C11', type is buried
!_LC5_C11 = _LC5_C11~NOT;
_LC5_C11~NOT = LCELL( _EQ014);
_EQ014 = _LC3_C11
# _LC7_C11
# !_LC2_C11
# !_LC1_C11;
Project Information f:\workhard\counter60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,556K
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