📄 counter6.rpt
字号:
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 09 AND2 0 3 0 1 |lpm_add_sub:45|addcore:adder|:59
- 4 - B 09 OR2 0 3 0 1 |lpm_add_sub:45|addcore:adder|:68
- 3 - B 09 OR2 ! 0 4 0 3 :14
- 1 - B 09 DFFE + 1 2 1 1 :41
- 8 - B 09 DFFE + 1 2 1 3 :42
- 2 - B 09 DFFE + 1 2 1 3 :43
- 6 - B 09 DFFE + 1 0 1 4 :44
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\workhard\counter6.rpt
counter6
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\workhard\counter6.rpt
counter6
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 CP
Device-Specific Information: f:\workhard\counter6.rpt
counter6
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 nCR
Device-Specific Information: f:\workhard\counter6.rpt
counter6
** EQUATIONS **
CP : INPUT;
EN : INPUT;
nCR : INPUT;
-- Node name is 'Q0'
-- Equation name is 'Q0', type is output
Q0 = _LC6_B9;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC2_B9;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC8_B9;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC1_B9;
-- Node name is '|lpm_add_sub:45|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ001);
_EQ001 = _LC2_B9 & _LC6_B9 & _LC8_B9;
-- Node name is '|lpm_add_sub:45|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = LCELL( _EQ002);
_EQ002 = !_LC2_B9 & _LC8_B9
# !_LC6_B9 & _LC8_B9
# _LC2_B9 & _LC6_B9 & !_LC8_B9;
-- Node name is ':14'
-- Equation name is '_LC3_B9', type is buried
!_LC3_B9 = _LC3_B9~NOT;
_LC3_B9~NOT = LCELL( _EQ003);
_EQ003 = !_LC8_B9
# _LC2_B9
# _LC1_B9
# !_LC6_B9;
-- Node name is ':41'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = DFFE( _EQ004, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ004 = _LC1_B9 & !_LC3_B9 & !_LC5_B9
# EN & !_LC1_B9 & !_LC3_B9 & _LC5_B9
# !EN & _LC1_B9;
-- Node name is ':42'
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = DFFE( _EQ005, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ005 = EN & !_LC3_B9 & _LC4_B9
# !EN & _LC8_B9;
-- Node name is ':43'
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = DFFE( _EQ006, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ006 = _LC2_B9 & !_LC3_B9 & !_LC6_B9
# EN & !_LC2_B9 & !_LC3_B9 & _LC6_B9
# !EN & _LC2_B9;
-- Node name is ':44'
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = DFFE( _EQ007, GLOBAL( CP), GLOBAL( nCR), VCC, VCC);
_EQ007 = EN & !_LC6_B9
# !EN & _LC6_B9;
Project Information f:\workhard\counter6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,025K
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