📄 complete_clock.rpt
字号:
- 1 - B 03 OR2 1 2 1 0 |_2to1MUX:MU1|:54
- 6 - A 23 OR2 1 2 1 0 |_2to1MUX:MU2|:26
- 4 - A 15 OR2 1 2 1 0 |_2to1MUX:MU2|:30
- 5 - A 23 OR2 1 2 1 0 |_2to1MUX:MU2|:34
- 7 - A 18 OR2 1 2 1 0 |_2to1MUX:MU2|:38
- 4 - A 17 OR2 1 2 1 0 |_2to1MUX:MU2|:42
- 1 - A 19 OR2 1 2 1 0 |_2to1MUX:MU2|:46
- 1 - A 24 OR2 1 2 1 0 |_2to1MUX:MU2|:50
- 3 - A 23 OR2 1 2 1 0 |_2to1MUX:MU2|:54
- 5 - A 11 AND2 1 1 1 0 |_2to1MUX:MU3|:28
- 6 - A 11 AND2 1 1 1 0 |_2to1MUX:MU3|:32
- 7 - C 01 AND2 1 1 1 0 |_2to1MUX:MU3|:36
- 3 - C 03 AND2 1 1 1 0 |_2to1MUX:MU3|:40
- 1 - C 06 AND2 1 1 1 0 |_2to1MUX:MU3|:44
- 6 - B 03 AND2 1 1 1 0 |_2to1MUX:MU3|:48
- 2 - B 03 AND2 1 1 1 0 |_2to1MUX:MU3|:52
- 7 - A 11 AND2 1 1 1 0 |_2to1MUX:MU3|:56
- 1 - A 04 OR2 0 4 1 0 :36
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: g:\workhard\complete_clock.rpt
complete_clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 16/ 96( 16%) 14/ 48( 29%) 16/ 48( 33%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
B: 20/ 96( 20%) 15/ 48( 31%) 29/ 48( 60%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 6/ 48( 12%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\workhard\complete_clock.rpt
complete_clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 40 CP
INPUT 3 _1kHz
Device-Specific Information: g:\workhard\complete_clock.rpt
complete_clock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 24 nCR
Device-Specific Information: g:\workhard\complete_clock.rpt
complete_clock
** EQUATIONS **
AdjHrkey : INPUT;
AdjMinkey : INPUT;
CP : INPUT;
CtrlBell : INPUT;
Mode : INPUT;
nCR : INPUT;
SetHrkey : INPUT;
SetMinkey : INPUT;
_1kHz : INPUT;
-- Node name is 'ALARM'
-- Equation name is 'ALARM', type is output
ALARM = _LC1_A4;
-- Node name is 'LED_Hr0'
-- Equation name is 'LED_Hr0', type is output
LED_Hr0 = _LC1_B3;
-- Node name is 'LED_Hr1'
-- Equation name is 'LED_Hr1', type is output
LED_Hr1 = _LC3_B23;
-- Node name is 'LED_Hr2'
-- Equation name is 'LED_Hr2', type is output
LED_Hr2 = _LC4_B3;
-- Node name is 'LED_Hr3'
-- Equation name is 'LED_Hr3', type is output
LED_Hr3 = _LC2_B22;
-- Node name is 'LED_Hr4'
-- Equation name is 'LED_Hr4', type is output
LED_Hr4 = _LC1_B20;
-- Node name is 'LED_Hr5'
-- Equation name is 'LED_Hr5', type is output
LED_Hr5 = _LC8_B20;
-- Node name is 'LED_Hr6'
-- Equation name is 'LED_Hr6', type is output
LED_Hr6 = _LC5_B17;
-- Node name is 'LED_Hr7'
-- Equation name is 'LED_Hr7', type is output
LED_Hr7 = _LC7_B17;
-- Node name is 'LED_Min0'
-- Equation name is 'LED_Min0', type is output
LED_Min0 = _LC3_A23;
-- Node name is 'LED_Min1'
-- Equation name is 'LED_Min1', type is output
LED_Min1 = _LC1_A24;
-- Node name is 'LED_Min2'
-- Equation name is 'LED_Min2', type is output
LED_Min2 = _LC1_A19;
-- Node name is 'LED_Min3'
-- Equation name is 'LED_Min3', type is output
LED_Min3 = _LC4_A17;
-- Node name is 'LED_Min4'
-- Equation name is 'LED_Min4', type is output
LED_Min4 = _LC7_A18;
-- Node name is 'LED_Min5'
-- Equation name is 'LED_Min5', type is output
LED_Min5 = _LC5_A23;
-- Node name is 'LED_Min6'
-- Equation name is 'LED_Min6', type is output
LED_Min6 = _LC4_A15;
-- Node name is 'LED_Min7'
-- Equation name is 'LED_Min7', type is output
LED_Min7 = _LC6_A23;
-- Node name is 'LED_Sec0'
-- Equation name is 'LED_Sec0', type is output
LED_Sec0 = _LC7_A11;
-- Node name is 'LED_Sec1'
-- Equation name is 'LED_Sec1', type is output
LED_Sec1 = _LC2_B3;
-- Node name is 'LED_Sec2'
-- Equation name is 'LED_Sec2', type is output
LED_Sec2 = _LC6_B3;
-- Node name is 'LED_Sec3'
-- Equation name is 'LED_Sec3', type is output
LED_Sec3 = _LC1_C6;
-- Node name is 'LED_Sec4'
-- Equation name is 'LED_Sec4', type is output
LED_Sec4 = _LC3_C3;
-- Node name is 'LED_Sec5'
-- Equation name is 'LED_Sec5', type is output
LED_Sec5 = _LC7_C1;
-- Node name is 'LED_Sec6'
-- Equation name is 'LED_Sec6', type is output
LED_Sec6 = _LC6_A11;
-- Node name is 'LED_Sec7'
-- Equation name is 'LED_Sec7', type is output
LED_Sec7 = _LC5_A11;
-- Node name is '|BaoShi:UC4|~27~1'
-- Equation name is '_LC1_A5', type is buried
-- synthesized logic cell
_LC1_A5 = LCELL( _EQ001);
_EQ001 = !_LC3_A5 & !_LC4_A10 & !_LC5_A10 & !_LC6_A5;
-- Node name is '|BaoShi:UC4|~27~2'
-- Equation name is '_LC1_A23', type is buried
-- synthesized logic cell
!_LC1_A23 = _LC1_A23~NOT;
_LC1_A23~NOT = LCELL( _EQ002);
_EQ002 = _LC2_A5
# _LC5_A5;
-- Node name is '|BaoShi:UC4|:27'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ003);
_EQ003 = _LC1_A5 & !_LC1_A10 & _LC1_A23 & !_LC3_A10;
-- Node name is '|BaoShi:UC4|~97~1'
-- Equation name is '_LC5_B3', type is buried
-- synthesized logic cell
_LC5_B3 = LCELL( _EQ004);
_EQ004 = _LC1_B15 & !_LC3_B8 & !_LC3_B15 & !_LC3_B21;
-- Node name is '|BaoShi:UC4|~116~1'
-- Equation name is '_LC6_B21', type is buried
-- synthesized logic cell
!_LC6_B21 = _LC6_B21~NOT;
_LC6_B21~NOT = LCELL( _EQ005);
_EQ005 = _LC1_B17 & !_LC4_B15 & !_LC6_B20;
-- Node name is '|BaoShi:UC4|~116~2'
-- Equation name is '_LC2_B21', type is buried
-- synthesized logic cell
!_LC2_B21 = _LC2_B21~NOT;
_LC2_B21~NOT = LCELL( _EQ006);
_EQ006 = !_LC2_B15 & _LC3_B15 & _LC3_B20 & !_LC6_B21
# _LC2_B15 & !_LC3_B15 & !_LC3_B20 & !_LC6_B21;
-- Node name is '|BaoShi:UC4|~221~1'
-- Equation name is '_LC8_B3', type is buried
-- synthesized logic cell
_LC8_B3 = LCELL( _EQ007);
_EQ007 = _LC1_B15 & !_LC2_B8 & !_LC2_B21
# _LC1_B15 & !_LC2_B21 & !_LC3_B8;
-- Node name is '|BaoShi:UC4|~302~1'
-- Equation name is '_LC3_B2', type is buried
-- synthesized logic cell
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ008);
_EQ008 = _LC1_B15 & !_LC3_B21;
-- Node name is '|BaoShi:UC4|~364~1'
-- Equation name is '_LC1_B21', type is buried
-- synthesized logic cell
!_LC1_B21 = _LC1_B21~NOT;
_LC1_B21~NOT = LCELL( _EQ009);
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