📄 complete_clock.rpt
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Average fan-in: 3.25/4 ( 81%)
Total fan-in: 546/2304 ( 23%)
Total input pins required: 9
Total input I/O cell registers required: 0
Total output pins required: 25
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 168
Total flipflops required: 41
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 55/ 576 ( 9%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 7 8 0 0 0 0 8 8 8 0 8 8 1 0 1 1 1 0 0 0 5 3 67/0
B: 2 8 8 0 0 0 8 8 0 0 0 0 0 8 0 8 8 8 1 0 7 7 1 8 8 98/0
C: 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3/0
Total: 3 8 9 7 8 1 8 8 0 8 8 8 0 16 8 9 8 9 2 1 7 7 1 13 11 168/0
Device-Specific Information: g:\workhard\complete_clock.rpt
complete_clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
17 - - A -- INPUT 0 0 0 1 AdjHrkey
84 - - - -- INPUT 0 0 0 2 AdjMinkey
43 - - - -- INPUT G 0 0 0 0 CP
71 - - A -- INPUT 0 0 0 1 CtrlBell
42 - - - -- INPUT 0 0 0 24 Mode
2 - - - -- INPUT G 0 0 0 0 nCR
44 - - - -- INPUT 0 0 0 8 SetHrkey
80 - - - 23 INPUT 0 0 0 4 SetMinkey
1 - - - -- INPUT G 0 0 0 2 _1kHz
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\workhard\complete_clock.rpt
complete_clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
16 - - A -- OUTPUT 0 1 0 0 ALARM
21 - - B -- OUTPUT 0 1 0 0 LED_Hr0
66 - - B -- OUTPUT 0 1 0 0 LED_Hr1
23 - - B -- OUTPUT 0 1 0 0 LED_Hr2
81 - - - 22 OUTPUT 0 1 0 0 LED_Hr3
67 - - B -- OUTPUT 0 1 0 0 LED_Hr4
25 - - B -- OUTPUT 0 1 0 0 LED_Hr5
65 - - B -- OUTPUT 0 1 0 0 LED_Hr6
64 - - B -- OUTPUT 0 1 0 0 LED_Hr7
72 - - A -- OUTPUT 0 1 0 0 LED_Min0
73 - - A -- OUTPUT 0 1 0 0 LED_Min1
52 - - - 19 OUTPUT 0 1 0 0 LED_Min2
51 - - - 18 OUTPUT 0 1 0 0 LED_Min3
69 - - A -- OUTPUT 0 1 0 0 LED_Min4
70 - - A -- OUTPUT 0 1 0 0 LED_Min5
49 - - - 16 OUTPUT 0 1 0 0 LED_Min6
78 - - - 24 OUTPUT 0 1 0 0 LED_Min7
19 - - A -- OUTPUT 0 1 0 0 LED_Sec0
22 - - B -- OUTPUT 0 1 0 0 LED_Sec1
24 - - B -- OUTPUT 0 1 0 0 LED_Sec2
27 - - C -- OUTPUT 0 1 0 0 LED_Sec3
28 - - C -- OUTPUT 0 1 0 0 LED_Sec4
30 - - C -- OUTPUT 0 1 0 0 LED_Sec5
3 - - - 12 OUTPUT 0 1 0 0 LED_Sec6
18 - - A -- OUTPUT 0 1 0 0 LED_Sec7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\workhard\complete_clock.rpt
complete_clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 05 AND2 s 0 4 0 1 |BaoShi:UC4|~27~1
- 1 - A 23 OR2 s ! 0 2 0 3 |BaoShi:UC4|~27~2
- 2 - A 04 AND2 0 4 0 1 |BaoShi:UC4|:27
- 5 - B 03 AND2 s 0 4 0 1 |BaoShi:UC4|~97~1
- 6 - B 21 AND2 s ! 0 3 0 2 |BaoShi:UC4|~116~1
- 2 - B 21 OR2 s ! 0 4 0 3 |BaoShi:UC4|~116~2
- 8 - B 03 OR2 s 0 4 0 1 |BaoShi:UC4|~221~1
- 3 - B 02 AND2 s ! 0 2 0 1 |BaoShi:UC4|~302~1
- 1 - B 21 OR2 s ! 0 4 0 1 |BaoShi:UC4|~364~1
- 3 - B 17 AND2 s ! 0 4 0 3 |BaoShi:UC4|~364~2
- 1 - B 02 AND2 0 2 0 1 |BaoShi:UC4|:364
- 4 - B 08 AND2 0 2 0 1 |BaoShi:UC4|:382
- 5 - B 02 AND2 0 2 0 1 |BaoShi:UC4|:426
- 6 - B 08 AND2 0 2 0 4 |BaoShi:UC4|:444
- 5 - B 08 OR2 0 4 0 1 |BaoShi:UC4|:504
- 6 - B 16 OR2 s ! 0 4 0 4 |BaoShi:UC4|~550~1
- 6 - B 02 OR2 s 0 4 0 1 |BaoShi:UC4|~593~1
- 5 - B 21 OR2 s ! 0 3 0 1 |BaoShi:UC4|~612~1
- 4 - B 21 AND2 s ! 0 4 0 3 |BaoShi:UC4|~612~2
- 2 - B 07 AND2 0 2 0 1 |BaoShi:UC4|:612
- 6 - B 07 OR2 0 4 0 1 |BaoShi:UC4|:685
- 3 - B 21 OR2 s ! 0 3 0 4 |BaoShi:UC4|~736~1
- 3 - B 07 AND2 s ! 0 2 0 2 |BaoShi:UC4|~736~2
- 7 - B 07 AND2 0 2 0 1 |BaoShi:UC4|:749
- 8 - B 07 OR2 s 0 4 0 1 |BaoShi:UC4|~779~1
- 5 - B 07 OR2 s 0 3 0 1 |BaoShi:UC4|~792~1
- 1 - B 07 AND2 s 0 2 0 1 |BaoShi:UC4|~792~2
- 2 - B 01 OR2 s 0 3 0 1 |BaoShi:UC4|~792~3
- 1 - B 01 AND2 s 0 3 0 1 |BaoShi:UC4|~792~4
- 7 - B 03 OR2 s 0 4 0 1 |BaoShi:UC4|~793~1
- 3 - B 03 OR2 s 0 4 0 1 |BaoShi:UC4|~793~2
- 4 - B 02 OR2 s 0 4 0 1 |BaoShi:UC4|~793~3
- 7 - B 02 OR2 s 0 4 0 1 |BaoShi:UC4|~793~4
- 8 - B 08 OR2 s 0 4 0 1 |BaoShi:UC4|~793~5
- 8 - B 02 OR2 s 0 4 0 1 |BaoShi:UC4|~793~6
- 2 - B 02 OR2 s 0 4 0 1 |BaoShi:UC4|~793~7
- 3 - A 11 AND2 s 0 4 0 1 |BaoShi:UC4|~793~8
- 4 - B 07 OR2 s 0 4 0 1 |BaoShi:UC4|~793~9
- 4 - A 04 OR2 s 0 4 0 1 |BaoShi:UC4|~793~10
- 5 - A 04 OR2 0 3 0 1 |BaoShi:UC4|:799
- 5 - B 13 AND2 s 0 4 0 1 |Bell:UC3|counter24:SU2|~104~1
- 2 - B 13 OR2 ! 0 3 0 1 |Bell:UC3|counter24:SU2|:134
- 5 - B 23 OR2 0 2 0 4 |Bell:UC3|counter24:SU2|:142
- 6 - B 24 AND2 s 0 4 0 3 |Bell:UC3|counter24:SU2|~150~1
- 4 - B 24 OR2 ! 0 4 0 3 |Bell:UC3|counter24:SU2|:156
- 8 - B 13 OR2 0 4 0 1 |Bell:UC3|counter24:SU2|:179
- 7 - B 13 OR2 0 3 0 1 |Bell:UC3|counter24:SU2|:180
- 2 - B 24 OR2 s 0 3 0 3 |Bell:UC3|counter24:SU2|~181~1
- 1 - B 23 OR2 0 3 0 1 |Bell:UC3|counter24:SU2|:181
- 4 - B 13 DFFE + 1 2 0 7 |Bell:UC3|counter24:SU2|:208
- 3 - B 13 DFFE + 1 2 0 8 |Bell:UC3|counter24:SU2|:209
- 8 - B 23 DFFE + 1 2 0 6 |Bell:UC3|counter24:SU2|:210
- 1 - B 24 DFFE + 1 1 0 5 |Bell:UC3|counter24:SU2|:211
- 8 - B 24 OR2 0 4 0 1 |Bell:UC3|counter24:SU2|:262
- 6 - B 13 OR2 s 0 4 0 1 |Bell:UC3|counter24:SU2|~274~1
- 1 - B 13 OR2 s 0 4 0 6 |Bell:UC3|counter24:SU2|~274~2
- 7 - B 24 OR2 s 0 3 0 1 |Bell:UC3|counter24:SU2|~275~1
- 4 - B 18 DFFE + 1 0 0 4 |Bell:UC3|counter24:SU2|:281
- 2 - B 17 DFFE + 1 0 0 4 |Bell:UC3|counter24:SU2|:282
- 3 - B 24 DFFE + 1 2 0 5 |Bell:UC3|counter24:SU2|:283
- 5 - B 24 DFFE + 1 2 0 6 |Bell:UC3|counter24:SU2|:284
- 6 - A 14 AND2 0 2 0 1 |Bell:UC3|counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 8 - A 14 AND2 0 3 0 1 |Bell:UC3|counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 5 - A 14 OR2 ! 0 4 0 3 |Bell:UC3|counter60:SU1|counter6:UC1|:14
- 1 - A 14 DFFE + 0 3 0 3 |Bell:UC3|counter60:SU1|counter6:UC1|:41
- 2 - A 14 DFFE + 0 3 0 4 |Bell:UC3|counter60:SU1|counter6:UC1|:42
- 4 - A 14 DFFE + 0 3 0 5 |Bell:UC3|counter60:SU1|counter6:UC1|:43
- 3 - A 14 DFFE + 0 1 0 6 |Bell:UC3|counter60:SU1|counter6:UC1|:44
- 8 - A 13 AND2 0 3 0 1 |Bell:UC3|counter60:SU1|counter10:UC0|lpm_add_sub:45|addcore:adder|:59
- 7 - A 13 OR2 0 3 0 1 |Bell:UC3|counter60:SU1|counter10:UC0|lpm_add_sub:45|addcore:adder|:68
- 6 - A 13 DFFE + 1 2 0 3 |Bell:UC3|counter60:SU1|counter10:UC0|:41
- 5 - A 13 DFFE + 1 2 0 5 |Bell:UC3|counter60:SU1|counter10:UC0|:42
- 3 - A 13 DFFE + 1 2 0 5 |Bell:UC3|counter60:SU1|counter10:UC0|:43
- 4 - A 13 DFFE + 1 0 0 6 |Bell:UC3|counter60:SU1|counter10:UC0|:44
- 1 - A 13 OR2 ! 0 4 0 7 |Bell:UC3|counter60:SU1|:12
- 8 - A 11 OR2 1 2 0 1 |Bell:UC3|:56
- 2 - B 20 OR2 s 0 4 0 1 |Bell:UC3|~59~1
- 2 - B 23 OR2 s 0 4 0 1 |Bell:UC3|~59~2
- 6 - B 17 OR2 s 0 4 0 1 |Bell:UC3|~59~3
- 2 - A 13 OR2 s 0 4 0 1 |Bell:UC3|~59~4
- 3 - A 24 OR2 s 0 4 0 1 |Bell:UC3|~59~5
- 2 - A 24 AND2 s 1 3 0 1 |Bell:UC3|~59~6
- 7 - A 14 OR2 s 0 4 0 1 |Bell:UC3|~59~7
- 2 - A 23 OR2 s 0 4 0 1 |Bell:UC3|~59~8
- 4 - B 23 OR2 s 0 4 0 1 |Bell:UC3|~59~9
- 6 - B 23 AND2 s 0 4 0 1 |Bell:UC3|~59~10
- 7 - B 23 AND2 0 4 0 1 |Bell:UC3|:59
- 4 - A 11 DFFE + 0 0 0 3 |Divided_Frequency:UC0|:5
- 2 - A 11 AND2 s 0 3 0 1 |Radio:UC2|~68~1
- 7 - A 04 OR2 1 3 0 1 |Radio:UC2|:82
- 7 - A 12 AND2 0 2 0 1 |top_clock:UC1|counter6:U2|lpm_add_sub:45|addcore:adder|:55
- 8 - A 12 AND2 0 3 0 1 |top_clock:UC1|counter6:U2|lpm_add_sub:45|addcore:adder|:59
- 2 - A 12 OR2 ! 0 4 0 7 |top_clock:UC1|counter6:U2|:14
- 3 - A 12 DFFE + 0 3 0 3 |top_clock:UC1|counter6:U2|:41
- 4 - A 12 DFFE + 0 3 0 4 |top_clock:UC1|counter6:U2|:42
- 6 - A 12 DFFE + 0 3 0 7 |top_clock:UC1|counter6:U2|:43
- 5 - A 12 DFFE + 0 1 0 12 |top_clock:UC1|counter6:U2|:44
- 7 - A 05 AND2 0 2 0 1 |top_clock:UC1|counter6:U4|lpm_add_sub:45|addcore:adder|:55
- 8 - A 05 AND2 0 3 0 1 |top_clock:UC1|counter6:U4|lpm_add_sub:45|addcore:adder|:59
- 4 - A 05 OR2 ! 0 3 0 3 |top_clock:UC1|counter6:U4|:14
- 2 - A 05 DFFE + 0 3 0 3 |top_clock:UC1|counter6:U4|:41
- 6 - A 05 DFFE + 0 3 0 6 |top_clock:UC1|counter6:U4|:42
- 5 - A 05 DFFE + 0 3 0 5 |top_clock:UC1|counter6:U4|:43
- 3 - A 05 DFFE + 0 1 0 8 |top_clock:UC1|counter6:U4|:44
- 7 - B 08 DFFE + 0 3 0 7 |top_clock:UC1|counter10:U1|:41
- 2 - B 08 DFFE + 0 3 0 7 |top_clock:UC1|counter10:U1|:42
- 3 - B 08 DFFE + 0 2 0 9 |top_clock:UC1|counter10:U1|:43
- 1 - A 11 DFFE + 0 0 0 8 |top_clock:UC1|counter10:U1|:44
- 7 - A 10 AND2 0 2 0 1 |top_clock:UC1|counter10:U3|lpm_add_sub:45|addcore:adder|:55
- 8 - A 10 AND2 0 3 0 1 |top_clock:UC1|counter10:U3|lpm_add_sub:45|addcore:adder|:59
- 2 - A 10 OR2 ! 0 4 0 5 |top_clock:UC1|counter10:U3|:14
- 5 - A 10 DFFE + 0 3 0 4 |top_clock:UC1|counter10:U3|:41
- 1 - A 10 DFFE + 0 3 0 5 |top_clock:UC1|counter10:U3|:42
- 3 - A 10 DFFE + 0 3 0 6 |top_clock:UC1|counter10:U3|:43
- 4 - A 10 DFFE + 0 1 0 7 |top_clock:UC1|counter10:U3|:44
- 3 - B 16 AND2 ! 0 2 0 3 |top_clock:UC1|counter24:U5|:58
- 1 - B 17 AND2 s 0 2 0 5 |top_clock:UC1|counter24:U5|~104~1
- 7 - B 16 AND2 0 3 0 2 |top_clock:UC1|counter24:U5|:134
- 8 - B 21 OR2 0 2 0 3 |top_clock:UC1|counter24:U5|:142
- 1 - B 16 AND2 s 0 2 0 1 |top_clock:UC1|counter24:U5|~150~1
- 8 - B 16 AND2 0 4 0 3 |top_clock:UC1|counter24:U5|:150
- 2 - B 16 OR2 ! 0 3 0 3 |top_clock:UC1|counter24:U5|:156
- 7 - B 15 OR2 0 3 0 1 |top_clock:UC1|counter24:U5|:180
- 5 - B 15 OR2 s 0 2 0 3 |top_clock:UC1|counter24:U5|~181~1
- 6 - B 15 OR2 0 3 0 1 |top_clock:UC1|counter24:U5|:181
- 8 - B 15 OR2 s 0 4 0 1 |top_clock:UC1|counter24:U5|~191~1
- 4 - B 15 DFFE + 0 3 0 10 |top_clock:UC1|counter24:U5|:208
- 3 - B 15 DFFE + 0 3 0 13 |top_clock:UC1|counter24:U5|:209
- 2 - B 15 DFFE + 0 3 0 9 |top_clock:UC1|counter24:U5|:210
- 1 - B 15 DFFE + 0 2 0 18 |top_clock:UC1|counter24:U5|:211
- 5 - B 20 OR2 0 4 0 1 |top_clock:UC1|counter24:U5|:262
- 4 - B 16 OR2 s 0 3 0 1 |top_clock:UC1|counter24:U5|~274~1
- 5 - B 16 OR2 s 0 4 0 6 |top_clock:UC1|counter24:U5|~274~2
- 4 - B 20 OR2 s 0 3 0 1 |top_clock:UC1|counter24:U5|~275~1
- 8 - B 17 DFFE + 0 1 0 4 |top_clock:UC1|counter24:U5|:281
- 4 - B 17 DFFE + 0 1 0 4 |top_clock:UC1|counter24:U5|:282
- 6 - B 20 DFFE + 0 3 0 9 |top_clock:UC1|counter24:U5|:283
- 3 - B 20 DFFE + 0 3 0 11 |top_clock:UC1|counter24:U5|:284
- 1 - B 08 OR2 ! 0 4 0 10 |top_clock:UC1|:29
- 6 - A 10 OR2 ! 1 2 0 4 |top_clock:UC1|:43
- 1 - A 12 OR2 ! 1 3 0 4 |top_clock:UC1|:69
- 3 - A 04 OR2 ! 1 3 0 8 |top_clock:UC1|:90
- 6 - A 04 OR2 s 0 4 0 2 |top_clock:UC1|~92~1
- 7 - B 17 OR2 1 2 1 0 |_2to1MUX:MU1|:26
- 5 - B 17 OR2 1 2 1 0 |_2to1MUX:MU1|:30
- 8 - B 20 OR2 1 2 1 0 |_2to1MUX:MU1|:34
- 1 - B 20 OR2 1 2 1 0 |_2to1MUX:MU1|:38
- 2 - B 22 OR2 1 2 1 0 |_2to1MUX:MU1|:42
- 4 - B 03 OR2 1 2 1 0 |_2to1MUX:MU1|:46
- 3 - B 23 OR2 1 2 1 0 |_2to1MUX:MU1|:50
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